[Mesa-dev] [PATCH 0/4] i965: Totally legit line width patches

[Kenneth Graunke]

Here are some totally legit line width patches.  I noticed that Cherryview
was setting line width in DW2 of 3DSTATE_SF, when it actually moved to DW1
at a different bit location.  While fixing that, I figured I should update
the clamp value to reflect the new hardware limit...which led me to want
to use ctx->Const.MaxLineWidth as the clamp value.  (There's actually a
TODO comment about this in the original Gen4 code.)  This then led me to
advertise a larger value for line widths.

No Piglit regressions on Gen4-7.5.  Which sounds comforting, except I think
we actually fail most of our line rendering tests anyway, so they wouldn't
have "regressed".  Plus, Piglit doesn't seem to test large line widths
in the first place.

I ran some oglconform tests which at least drew things with larger line
widths, but I'm not sure how to view the output, and they didn't appear
to actually probe values and fail the test when wrong.

Also untested on Broadwell, Cherryview, or Skylake, which is kind of the
point of the series.  This is high quality stuff, folks!

Suggestions of "please write Piglit tests" will be tacitly ignored/filed
away in the "when I get to it (but I'll probably forget first)" file. :)