[Mesa-dev] [PATCH 2/2] i965: Remove non-existent vertical strides from array.
Kenneth Graunke
kenneth at whitecape.org
Wed Nov 5 02:22:49 PST 2014
On Friday, October 31, 2014 05:47:14 PM Matt Turner wrote:
> These never existed, as far as I can tell.
> ---
> src/mesa/drivers/dri/i965/brw_eu_emit.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> index bb6334b..b611e77 100644
> --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> @@ -227,7 +227,7 @@ static void
> validate_reg(const struct brw_context *brw, brw_inst *inst, struct brw_reg
reg)
> {
> int hstride_for_reg[] = {0, 1, 2, 4};
> - int vstride_for_reg[] = {0, 1, 2, 4, 8, 16, 32, 64, 128, 256};
> + int vstride_for_reg[] = {0, 1, 2, 4, 8, 16, 32};
> int width_for_reg[] = {1, 2, 4, 8, 16};
> int execsize_for_reg[] = {1, 2, 4, 8, 16};
> int width, hstride, vstride, execsize;
>
965 volume 4 page 371 agrees with you:
"Vertical Stride. [...]
Encoding of this field provides values in power of 2, ranging from 0 to 32
elements. Larger values are not supported due to the restriction that a
source operand must reside within two adjacent 256-bit registers (64 bytes
total).
Special encoding 1111b (0xF) is [...]"
Both patches are:
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
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