[Mesa-dev] [PATCH] i965: Use the predicate enable bit for conditional rendering without stalling

Neil Roberts neil at linux.intel.com
Mon Nov 10 11:42:22 PST 2014

Neil Roberts <neil at linux.intel.com> writes:

> It looks like the PRM for Haswell says that MI_LOAD_REGISTER_MEM is
> converted to no-op for non-privileged buffers. However I can't find any
> mention of this for IvyBridge. Does that mean it's allowed on IvyBridge
> but it won't work on Haswell? I haven't tested it on Haswell yet.

Ok, I just tested it on Haswell and sure enough it doesn't work. It does
however fail gracefully because can_do_pipelined_register_writes fails
so it doesn't even try to use the predicate registers. I think in that
case it wouldn't cause any problems to land the patches as they are. If
we later find a way to make it work on Haswell we could bump the command
parser version again as you say. We could also use that when deciding
whether to enable indirect rendering to avoid having to do a trial load.

- Neil

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