[Mesa-dev] [PATCH 3/4] i965/vec4: Combine all the math emitters.

[Kenneth Graunke]

On Wednesday, November 12, 2014 09:57:30 PM Matt Turner wrote:
> On Wed, Nov 12, 2014 at 9:35 PM, Kenneth Graunke <kenneth at whitecape.org> 
wrote:
> > +vec4_visitor::emit_math(enum opcode opcode,
> > +                       dst_reg dst, src_reg src0, src_reg src1)
> 
> I think you can make the arguments const references too?

Yeah.  I've changed the prototype to:

void emit_math(enum opcode opcode, const dst_reg &dst, const src_reg &src0,
               const src_reg &src1 = src_reg());

It also meant changing the first few lines to:

   vec4_instruction *math =
      emit(opcode, dst, fix_math_operand(src0), fix_math_operand(src1))

since "src0 = fix_math_operand(src0)" doesn't work with "const src_reg &".

> > +   if (brw->gen == 6 && dst.writemask != WRITEMASK_XYZW) {
> > +      /* MATH on Gen6 must be align1, so we can't do writemasks. */
> > +      math->dst = dst_reg(this, glsl_type::vec4_type);
> > +      math->dst.type = dst.type;
> > +      math->dst.writemask = WRITEMASK_XYZW;
> 
> I don't think you need to set the writemask (XYZW is the default).

I do, actually - it's guaranteed to not be XYZW at this point.  The caller 
passed us a destination register with some writemask set.  We create the 
"math" instruction using dst, so it inherits that writemask.  This block 
executes when dst.writemask != WRITEMASK_XYZW.

The point is to override it back to XYZW, since it isn't.

> > +      emit(MOV(dst, src_reg(math->dst)));
> > +   } else if (brw->gen < 6) {
> > +      math->base_mrf = 1;
> > +      math->mlen = src1.file == BAD_FILE ? 1 : 2;
> >     }
> >  }
> 
> Series is
> 
> Reviewed-by: Matt Turner <mattst88 at gmail.com>

Thanks!
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