[Mesa-dev] [PATCH 1/2] i965: Assert that math instructions don't have conditional mod.

[Kenneth Graunke]

On Friday, November 21, 2014 12:41:25 PM Matt Turner wrote:
> ---
> Strangely, the suggested implementations of double-precision sqrt/rcp
> in the BSpec show using a math instruction with an "eo" conditional
> modifier. I have no idea what that could possibly mean, or how it could
> work since conditional mod shares the same four bits with math SFID.

I'm confused - what generation of hardware are you talking about?
The MATH instruction doesn't have an SFID on Gen6+...only Gen4-5, where
it was a message.  But I wasn't aware double precision was even remotely
possible on Gen4-5.

> 
>  src/mesa/drivers/dri/i965/brw_fs_generator.cpp   | 2 ++
>  src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 2 ++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> index ab5d223..4af9cbe 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> @@ -1817,6 +1817,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
>        case SHADER_OPCODE_SIN:
>        case SHADER_OPCODE_COS:
>           assert(brw->gen < 6 || inst->mlen == 0);
> +         assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
>  	 if (brw->gen >= 7) {
>              gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
>                        brw_null_reg());
> @@ -1832,6 +1833,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
>        case SHADER_OPCODE_INT_REMAINDER:
>        case SHADER_OPCODE_POW:
>           assert(brw->gen < 6 || inst->mlen == 0);
> +         assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
>  	 if (brw->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
>              gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
>  	 } else if (brw->gen >= 6) {
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> index 0776a91..d027fda 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> @@ -1361,6 +1361,7 @@ vec4_generator::generate_code(const cfg_t *cfg)
>        case SHADER_OPCODE_LOG2:
>        case SHADER_OPCODE_SIN:
>        case SHADER_OPCODE_COS:
> +         assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
>           if (brw->gen >= 7) {
>              gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
>                        brw_null_reg());
> @@ -1374,6 +1375,7 @@ vec4_generator::generate_code(const cfg_t *cfg)
>        case SHADER_OPCODE_POW:
>        case SHADER_OPCODE_INT_QUOTIENT:
>        case SHADER_OPCODE_INT_REMAINDER:
> +         assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
>           if (brw->gen >= 7) {
>              gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
>           } else if (brw->gen == 6) {
> 
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