[Mesa-dev] [PATCH] radeonsi: use minnum and maxnum LLVM intrinsics for MIN and MAX opcodes
Marek Olšák
maraeo at gmail.com
Sat Nov 22 04:35:28 PST 2014
AFAICS, the R600 backend doesn't implement the intrinsics for R600.
Marek
On Sat, Nov 22, 2014 at 3:53 AM, Michel Dänzer <michel at daenzer.net> wrote:
> On 21.11.2014 06:21, Marek Olšák wrote:
>>
>> From: Marek Olšák <marek.olsak at amd.com>
>>
>> So far it has been compiled into pretty ugly code (8 instructions or so
>> for either opcode).
>> ---
>> src/gallium/drivers/radeonsi/si_shader.c | 7 +++++++
>> 1 file changed, 7 insertions(+)
>>
>> diff --git a/src/gallium/drivers/radeonsi/si_shader.c
>> b/src/gallium/drivers/radeonsi/si_shader.c
>> index ee08d1a..973bac2 100644
>> --- a/src/gallium/drivers/radeonsi/si_shader.c
>> +++ b/src/gallium/drivers/radeonsi/si_shader.c
>> @@ -2792,6 +2792,13 @@ int si_shader_create(struct si_screen *sscreen,
>> struct si_shader *shader)
>> bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
>> bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit =
>> si_llvm_emit_primitive;
>>
>> + if (HAVE_LLVM >= 0x0306) {
>> + bld_base->op_actions[TGSI_OPCODE_MAX].emit =
>> build_tgsi_intrinsic_nomem;
>> + bld_base->op_actions[TGSI_OPCODE_MAX].intr_name =
>> "llvm.maxnum.f32";
>> + bld_base->op_actions[TGSI_OPCODE_MIN].emit =
>> build_tgsi_intrinsic_nomem;
>> + bld_base->op_actions[TGSI_OPCODE_MIN].intr_name =
>> "llvm.minnum.f32";
>> + }
>> +
>> si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
>> si_shader_ctx.tokens = sel->tokens;
>> tgsi_parse_init(&si_shader_ctx.parse, si_shader_ctx.tokens);
>>
>
> Shouldn't this be done in
> src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c, so it benefits r600g as
> well?
>
>
> --
> Earthling Michel Dänzer | http://www.amd.com
> Libre software enthusiast | Mesa and X developer
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