[Mesa-dev] [PATCH] gallivm: force sse instructions for llvm 3.5+

[Ilia Mirkin]

On Thu, Oct 2, 2014 at 11:34 AM, Jose Fonseca <jfonseca at vmware.com> wrote:
> On 02/10/14 03:09, Ilia Mirkin wrote:
>>
>> On Wed, Oct 1, 2014 at 10:56 AM, Maarten Lankhorst
>> <maarten at mblankhorst.nl> wrote:
>>>
>>> This fixes a crash when llvmpipe tries to use sse instructions,
>>> but llvm detects a cpu that doesn't support them.
>>>
>>> Fixes for example piglit/bin/amd_seamless_cubemap_per_texture -fbo -auto
>>> on i386 when run inside "qemu -cpu qemu32", which would otherwise error
>>> with:
>>> "LLVM ERROR: Do not know how to split the result of this operator!"
>>>
>>> Signed-off-by: Maarten Lankhorst <maarten.lankhorst at canonical.com>
>>> ---
>>>
>>> diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
>>> b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
>>> index 55aa8b9..f2f8906 100644
>>> --- a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
>>> +++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
>>> @@ -479,10 +479,38 @@
>>> lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT,
>>>         if (util_cpu_caps.has_f16c) {
>>>            MAttrs.push_back("+f16c");
>>>         }
>>> -      builder.setMAttrs(MAttrs);
>>>      }
>>>
>>>   #if HAVE_LLVM >= 0x0305
>>> +   /*
>>> +    * llvm 3.5 no longer supports cpuid based autodetect.
>>> +    * This breaks on "qemu -cpu qemu32" which is detected as pentium2 by
>>> llvm's
>>> +    * sys::getHostCPUName(), but does support sse2.
>>> +    *
>>> +    * For this reason force the use of sse extensions when available, so
>>> our
>>> +    * understanding of the cpu is in sync with llvm's.
>>> +    */
>>> +
>>> +   else if (util_cpu_caps.has_sse4_2)
>>> +      MAttrs.push_back("+sse42");
>>> +   else if (util_cpu_caps.has_sse4_1)
>>> +      MAttrs.push_back("+sse41");
>>> +   else if (util_cpu_caps.has_ssse3)
>>> +      MAttrs.push_back("+ssse3");
>>> +   else if (util_cpu_caps.has_sse3)
>>> +      MAttrs.push_back("+sse3");
>>> +   else if (util_cpu_caps.has_sse2)
>>> +      MAttrs.push_back("+sse2");
>>> +   else if (util_cpu_caps.has_sse)
>>> +      MAttrs.push_back("+sse");
>>> +   else if (util_cpu_caps.has_mmx)
>>> +      MAttrs.push_back("+sse");
>>
>>
>> I'm not familiar with LLVM, but if this isn't a typo (i.e. "+mmx"),
>> this probably deserves a comment. Also does +sse42 imply all the other
>> "lower" SSE instructions?
>
>
> Actually, I think it's better not to enable MMX, 3DNow, or anything that
> operates on XMM registers, as mixing code that operates on SSE and MMX
> registers is complicated and inefficient.

If you made it this far into the else chain, you don't have XMM registers...