[Mesa-dev] [PATCH] i965/fs: Use the correct base_mrf for spilling pairs in SIMD8

[Matt Turner]

On Thu, Oct 2, 2014 at 4:16 PM, Jason Ekstrand <jason at jlekstrand.net> wrote:
> Before, we were hard-coding the base_mrf based on dispatch width not number
> of registers spilled at a time.  This caused us to emit instructions with a
> base_mrf or 14 and a mlen of 3 so we used the magical non-existant m16
> register.  This fixes the problem.
> ---
>  src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
> index 176f91e..32669f6 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
> @@ -656,11 +656,12 @@ void
>  fs_visitor::emit_spill(bblock_t *block, fs_inst *inst, fs_reg src,
>                         uint32_t spill_offset, int count)
>  {
> -   int spill_base_mrf = dispatch_width > 8 ? 13 : 14;
> -
>     int reg_size = 1;
> -   if (count % 2 == 0)
> +   int spill_base_mrf = 14;
> +   if (count % 2 == 0) {
> +      spill_base_mrf = 13;
>        reg_size = 2;
> +   }
>
>     for (int i = 0; i < count / reg_size; i++) {
>        fs_inst *spill_inst =
> --
> 2.1.0

I'm not sure I understand enough but I trust that you do, so have a

Tested-by: Matt Turner <mattst88 at gmail.com>