[Mesa-dev] [WIP 11/25] i965/fs: Prepare register allocator for double precision floats

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
 src/mesa/drivers/dri/i965/brw_fs.h                |  1 +
 src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 29 +++++++++++++++++++++++
 2 files changed, 30 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index 09ac1eb..8c11c32 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -417,6 +417,7 @@ public:
                                    int first_payload_node);
    void setup_mrf_hack_interference(struct ra_graph *g,
                                     int first_mrf_hack_node);
+   void setup_double_float_interference(struct ra_graph *g);
    int choose_spill_reg(struct ra_graph *g);
    void spill_reg(int spill_reg);
    void split_virtual_grfs();
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index 65a09a0..05da88b 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -459,6 +459,32 @@ fs_visitor::setup_mrf_hack_interference(struct ra_graph *g, int first_mrf_node)
    }
 }
 
+/**
+ * Double precision floats require the hardware to execute two instructions
+ * in order to produce results for execution width many channels. If the
+ * register regions overlap for source and destination the first instruction
+ * may overwrite one of the sources needed by the second instruction.
+ * This can be prevented by telling the register allocator to use
+ * non-overlapping regions.
+ */
+void
+fs_visitor::setup_double_float_interference(struct ra_graph *g)
+{
+   foreach_block_and_inst(block, fs_inst, inst, cfg) {
+      if (inst->dst.file != GRF)
+         continue;
+
+      if (inst->dst.type != BRW_REGISTER_TYPE_DF)
+         continue;
+
+      for (int i = 0; i < inst->sources; ++i) {
+         if (inst->src[i].file == GRF) {
+            ra_add_node_interference(g, inst->dst.reg, inst->src[i].reg);
+         }
+      }
+   }
+}
+
 bool
 fs_visitor::assign_regs(bool allow_spilling)
 {
@@ -540,6 +566,9 @@ fs_visitor::assign_regs(bool allow_spilling)
       }
    }
 
+   if (brw->gen >= 7)
+      setup_double_float_interference(g);
+
    if (dispatch_width > 8) {
       /* In 16-wide dispatch we have an issue where a compressed
        * instruction is actually two instructions executed simultaneiously.
-- 
1.8.3.1