[Mesa-dev] [WIP 22/25] i965: Add helper telling if uniform is double and requires special load

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
 src/mesa/drivers/dri/i965/brw_shader.cpp | 36 ++++++++++++++++++++++++++++++++
 src/mesa/drivers/dri/i965/brw_shader.h   |  2 ++
 2 files changed, 38 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 0d8cddc..4a02c5b 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -927,3 +927,39 @@ backend_visitor::assign_common_binding_table_offsets(uint32_t next_binding_table
 
    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
 }
+
+/**
+ * Check if double precision scalar needs to be loaded into vector - IVB
+ * can operate only with scalars of single precision.
+ *
+ * Quotes from the docs:
+ *
+ * IVB PRM vol4 part 3, section 3.1 (about align1 mode):
+ * "A single precision float scalar is allowed."
+ *
+ * Section 3.3.9 (Register region restrictions):
+ * "If ExecSize = Width = 1, both VertStride and HorzStride must be 0. This
+ *  defines a scalar."
+ * "If VertStride = HorzStride = 0, Width must be 1 regardless of the value
+ *  of ExecSize."
+ *
+ * "In Align1 mode, all regioning parameters like stride, execution size, and
+ *  width must use the syntax of a pair of packed floats. The offsets for
+ *  these data types must be 64 - bit aligned. The execution size and
+ *  regioning parameters are in terms of floats.
+ *
+ *    Example: mov (8) r10.0<1>:df r11.0<8;8,1>:df
+ *    The above instruction moves four double floats"
+ *
+ * Hence in case of "double scalar", one should set width = 2 violating the
+ * second constraint.
+ */
+bool
+backend_visitor::is_df_uniform_and_needs_separate_load(
+   const struct backend_reg& reg) const
+{
+   if (brw->gen >= 8 || brw->is_haswell)
+      return false;
+
+   return reg.file == UNIFORM && reg.type == BRW_REGISTER_TYPE_DF; 
+}
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h
index f0d4f85..7ae833a 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -180,6 +180,8 @@ public:
    void assign_common_binding_table_offsets(uint32_t next_binding_table_offset);
 
    virtual void invalidate_live_intervals() = 0;
+
+   bool is_df_uniform_and_needs_separate_load(const backend_reg& reg) const;
 };
 
 uint32_t brw_texture_offset(struct gl_context *ctx, ir_constant *offset);
-- 
1.8.3.1