[Mesa-dev] [PATCH 2/5] i965/fs: Don't [un]spill multiple registers at a time in SIMD8 mode

[Jason Ekstrand]

I thought this would be a clever way to make spilling less expensive.
However, it appears that the oword read/write messages we are using for
spilling ignore the execution size and assume SIMD16 whenever working with
more than one register.
---
 src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index 65a09a0..d4b72d8 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -625,8 +625,10 @@ fs_visitor::emit_unspill(bblock_t *block, fs_inst *inst, fs_reg dst,
                          uint32_t spill_offset, int count)
 {
    int reg_size = 1;
-   if (count % 2 == 0)
+   if (dispatch_width == 16 && count % 2 == 0) {
       reg_size = 2;
+      dst.width = 16;
+   }
 
    for (int i = 0; i < count / reg_size; i++) {
       /* The gen7 descriptor-based offset is 12 bits of HWORD units. */
@@ -659,7 +661,7 @@ fs_visitor::emit_spill(bblock_t *block, fs_inst *inst, fs_reg src,
 {
    int reg_size = 1;
    int spill_base_mrf = 14;
-   if (count % 2 == 0) {
+   if (dispatch_width == 16 && count % 2 == 0) {
       spill_base_mrf = 13;
       reg_size = 2;
    }
-- 
2.1.0