[Mesa-dev] [PATCH 05/14] i965: Add SIMD8 URB write low-level IR instruction

[Kristian Høgsberg]

On Tue, Oct 28, 2014 at 4:17 PM, Matt Turner <mattst88 at gmail.com> wrote:
> On Tue, Oct 28, 2014 at 3:17 PM, Kristian Høgsberg <krh at bitplanet.net> wrote:
>> This is all we need from the generator for SIMD8 vertex shaders.  This
>> opcode is just the send instruction, all the hard work will happen
>> in the visitor using LOAD_PAYLOAD.
>>
>> Signed-off-by: Kristian Høgsberg <krh at bitplanet.net>
>> ---
>>  src/mesa/drivers/dri/i965/brw_defines.h           |  1 +
>>  src/mesa/drivers/dri/i965/brw_fs.cpp              |  4 ++++
>>  src/mesa/drivers/dri/i965/brw_fs.h                |  1 +
>>  src/mesa/drivers/dri/i965/brw_fs_generator.cpp    | 25 +++++++++++++++++++++++
>>  src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 16 ++++++++++++++-
>>  src/mesa/drivers/dri/i965/brw_shader.cpp          |  1 +
>>  6 files changed, 47 insertions(+), 1 deletion(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
>> index ab45d3d..bc7304b 100644
>> --- a/src/mesa/drivers/dri/i965/brw_defines.h
>> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
>> @@ -1520,6 +1520,7 @@ enum brw_message_target {
>>
>>  #define BRW_URB_OPCODE_WRITE_HWORD  0
>>  #define BRW_URB_OPCODE_WRITE_OWORD  1
>> +#define BRW_URB_OPCODE_SIMD8_WRITE  7
>
> BSpec is failing me -- if this is Gen8+, prefix with GEN8 rather than BRW.

It is, I'll fix the prefix.

>>
>>  #define BRW_URB_SWIZZLE_NONE          0
>>  #define BRW_URB_SWIZZLE_INTERLEAVE    1
>> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
>> index 97fefff..815c8c2 100644
>> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
>> @@ -509,6 +509,7 @@ fs_inst::is_send_from_grf() const
>>     case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
>>     case SHADER_OPCODE_UNTYPED_ATOMIC:
>>     case SHADER_OPCODE_UNTYPED_SURFACE_READ:
>> +   case VS_OPCODE_URB_WRITE:
>
> Presumably we'll do SIMD8 geometry shaders (and tessellation in the
> future?). As a follow on, could we consolidate [GV]S_OPCODE_URB_WRITE
> into one SHADER_OPCODE_URB_WRITE?

Yeah, good point, I'll just update the opcode now.

Kristian