[Mesa-dev] [PATCH 06/14] i965: Add brw_scalar_prog_data structure
Jordan Justen
jordan.l.justen at intel.com
Mon Sep 1 09:44:30 PDT 2014
All fields were migrated from brw_wm_prog_data. In future updates, we can move
these FS specific fields back into brw_wm_prog_data.
The scalar_visitor and scalar_generator class mainly use these structures now.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
---
src/mesa/drivers/dri/i965/Makefile.sources | 1 +
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_context.h | 13 +++++--
src/mesa/drivers/dri/i965/brw_curbe.c | 6 +--
src/mesa/drivers/dri/i965/brw_fs.cpp | 8 ++--
src/mesa/drivers/dri/i965/brw_scalar.c | 43 ++++++++++++++++++++++
src/mesa/drivers/dri/i965/brw_scalar.h | 7 ++--
src/mesa/drivers/dri/i965/brw_scalar_generator.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_scalar_visitor.cpp | 4 +-
src/mesa/drivers/dri/i965/brw_wm.c | 17 +++++----
src/mesa/drivers/dri/i965/brw_wm.h | 2 +-
src/mesa/drivers/dri/i965/brw_wm_state.c | 28 +++++++-------
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 10 ++---
src/mesa/drivers/dri/i965/gen6_clip_state.c | 2 +-
src/mesa/drivers/dri/i965/gen6_sf_state.c | 4 +-
src/mesa/drivers/dri/i965/gen6_surface_state.c | 2 +-
src/mesa/drivers/dri/i965/gen6_wm_state.c | 34 ++++++++---------
src/mesa/drivers/dri/i965/gen7_sf_state.c | 2 +-
src/mesa/drivers/dri/i965/gen7_wm_state.c | 36 +++++++++---------
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 4 +-
src/mesa/drivers/dri/i965/gen8_ps_state.c | 32 ++++++++--------
src/mesa/drivers/dri/i965/gen8_sf_state.c | 2 +-
src/mesa/drivers/dri/i965/gen8_surface_state.c | 4 +-
23 files changed, 160 insertions(+), 105 deletions(-)
create mode 100644 src/mesa/drivers/dri/i965/brw_scalar.c
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources
index 08d0b38..8461975 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -82,6 +82,7 @@ i965_FILES = \
brw_queryobj.c \
brw_reset.c \
brw_sampler_state.c \
+ brw_scalar.c \
brw_scalar_generator.cpp \
brw_scalar_visitor.cpp \
brw_schedule_instructions.cpp \
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
index 82ece73..e04dfd5 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
@@ -31,7 +31,7 @@ brw_blorp_eu_emitter::brw_blorp_eu_emitter(struct brw_context *brw,
: mem_ctx(ralloc_context(NULL)),
generator(brw, mem_ctx,
rzalloc(mem_ctx, struct brw_wm_prog_key),
- rzalloc(mem_ctx, struct brw_wm_prog_data),
+ (brw_scalar_prog_data*) rzalloc(mem_ctx, struct brw_wm_prog_data),
NULL, NULL, false, debug_flag)
{
}
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 602275c..bd9c25d 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -147,7 +147,7 @@ struct brw_inst;
struct brw_vs_prog_key;
struct brw_vec4_prog_key;
struct brw_wm_prog_key;
-struct brw_wm_prog_data;
+struct brw_scalar_prog_data;
enum brw_state_id {
BRW_STATE_URB_FENCE,
@@ -319,10 +319,10 @@ struct brw_stage_prog_data {
* corresponding to a different brw_wm_prog_key struct, with different
* compiled programs.
*
- * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
+ * Note: brw_scalar_prog_data_compare() must be updated when adding fields to this
* struct!
*/
-struct brw_wm_prog_data {
+struct brw_scalar_prog_data {
struct brw_stage_prog_data base;
GLuint curb_read_length;
@@ -361,6 +361,13 @@ struct brw_wm_prog_data {
int urb_setup[VARYING_SLOT_MAX];
};
+/* Note: brw_wm_prog_data_compare() must be updated when adding fields to this
+ * struct!
+ */
+struct brw_wm_prog_data {
+ struct brw_scalar_prog_data base;
+};
+
/**
* Enum representing the i965-specific vertex results that don't correspond
* exactly to any element of gl_varying_slot. The values of this enum are
diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c
index 1a828ed..98909ac 100644
--- a/src/mesa/drivers/dri/i965/brw_curbe.c
+++ b/src/mesa/drivers/dri/i965/brw_curbe.c
@@ -76,7 +76,7 @@ static void calculate_curbe_offsets( struct brw_context *brw )
{
struct gl_context *ctx = &brw->ctx;
/* CACHE_NEW_WM_PROG */
- const GLuint nr_fp_regs = (brw->wm.prog_data->base.nr_params + 15) / 16;
+ const GLuint nr_fp_regs = (brw->wm.prog_data->base.base.nr_params + 15) / 16;
/* CACHE_NEW_VS_PROG */
const GLuint nr_vp_regs = (brw->vs.prog_data->base.base.nr_params + 15) / 16;
@@ -215,8 +215,8 @@ brw_upload_constant_buffer(struct brw_context *brw)
GLuint offset = brw->curbe.wm_start * 16;
/* CACHE_NEW_WM_PROG | _NEW_PROGRAM_CONSTANTS: copy uniform values */
- for (i = 0; i < brw->wm.prog_data->base.nr_params; i++) {
- buf[offset + i] = *brw->wm.prog_data->base.param[i];
+ for (i = 0; i < brw->wm.prog_data->base.base.nr_params; i++) {
+ buf[offset + i] = *brw->wm.prog_data->base.base.param[i];
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 179a06f..e1618fe 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -3373,13 +3373,15 @@ const unsigned *
brw_wm_fs_emit(struct brw_context *brw,
void *mem_ctx,
const struct brw_wm_prog_key *key,
- struct brw_wm_prog_data *prog_data,
+ struct brw_wm_prog_data *wm_prog_data,
struct gl_fragment_program *fp,
struct gl_shader_program *prog,
unsigned *final_assembly_size)
{
bool start_busy = false;
double start_time = 0;
+ struct brw_scalar_prog_data *prog_data =
+ (brw_scalar_prog_data*)wm_prog_data;
if (unlikely(brw->perf_debug)) {
start_busy = (brw->batch.last_bo &&
@@ -3396,7 +3398,7 @@ brw_wm_fs_emit(struct brw_context *brw,
/* Now the main event: Visit the shader IR and generate our FS IR for it.
*/
- scalar_visitor v(brw, mem_ctx, key, prog_data, prog, fp, 8);
+ scalar_visitor v(brw, mem_ctx, key, wm_prog_data, prog, fp, 8);
if (!v.run()) {
if (prog) {
prog->LinkStatus = false;
@@ -3410,7 +3412,7 @@ brw_wm_fs_emit(struct brw_context *brw,
}
cfg_t *simd16_cfg = NULL;
- scalar_visitor v2(brw, mem_ctx, key, prog_data, prog, fp, 16);
+ scalar_visitor v2(brw, mem_ctx, key, wm_prog_data, prog, fp, 16);
if (brw->gen >= 5 && likely(!(INTEL_DEBUG & DEBUG_NO16))) {
if (!v.simd16_unsupported) {
/* Try a SIMD16 compile */
diff --git a/src/mesa/drivers/dri/i965/brw_scalar.c b/src/mesa/drivers/dri/i965/brw_scalar.c
new file mode 100644
index 0000000..c7772b7
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/brw_scalar.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "brw_scalar.h"
+
+bool
+brw_scalar_prog_data_compare(const void *in_a, const void *in_b)
+{
+ const struct brw_scalar_prog_data *a = in_a;
+ const struct brw_scalar_prog_data *b = in_b;
+
+ /* Compare the base structure. */
+ if (!brw_stage_prog_data_compare(&a->base, &b->base))
+ return false;
+
+ /* Compare the rest of the structure. */
+ const unsigned offset = sizeof(struct brw_stage_prog_data);
+ if (memcmp(((char *) a) + offset, ((char *) b) + offset,
+ sizeof(struct brw_scalar_prog_data) - offset))
+ return false;
+
+ return true;
+}
diff --git a/src/mesa/drivers/dri/i965/brw_scalar.h b/src/mesa/drivers/dri/i965/brw_scalar.h
index be71101..b5d4372 100644
--- a/src/mesa/drivers/dri/i965/brw_scalar.h
+++ b/src/mesa/drivers/dri/i965/brw_scalar.h
@@ -482,7 +482,7 @@ public:
struct gl_fragment_program *fp;
const struct brw_wm_prog_key *const key;
- struct brw_wm_prog_data *prog_data;
+ struct brw_scalar_prog_data *prog_data;
unsigned int sanity_param_count;
int *param_size;
@@ -585,7 +585,7 @@ public:
scalar_generator(struct brw_context *brw,
void *mem_ctx,
const struct brw_wm_prog_key *key,
- struct brw_wm_prog_data *prog_data,
+ struct brw_scalar_prog_data *prog_data,
struct gl_shader_program *prog,
struct gl_fragment_program *fp,
bool runtime_check_aads_emit,
@@ -691,7 +691,7 @@ private:
struct brw_compile *p;
const struct brw_wm_prog_key *const key;
- struct brw_wm_prog_data *prog_data;
+ struct brw_scalar_prog_data *prog_data;
struct gl_shader_program *prog;
const struct gl_fragment_program *fp;
@@ -711,3 +711,4 @@ struct brw_reg brw_reg_from_fs_reg(fs_reg *reg);
bool brw_do_channel_expressions(struct exec_list *instructions);
bool brw_do_vector_splitting(struct exec_list *instructions);
bool brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog);
+bool brw_scalar_prog_data_compare(const void *in_a, const void *in_b);
diff --git a/src/mesa/drivers/dri/i965/brw_scalar_generator.cpp b/src/mesa/drivers/dri/i965/brw_scalar_generator.cpp
index a5a5cad..74c5b79 100644
--- a/src/mesa/drivers/dri/i965/brw_scalar_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_scalar_generator.cpp
@@ -39,7 +39,7 @@ extern "C" {
scalar_generator::scalar_generator(struct brw_context *brw,
void *mem_ctx,
const struct brw_wm_prog_key *key,
- struct brw_wm_prog_data *prog_data,
+ struct brw_scalar_prog_data *prog_data,
struct gl_shader_program *prog,
struct gl_fragment_program *fp,
bool runtime_check_aads_emit,
diff --git a/src/mesa/drivers/dri/i965/brw_scalar_visitor.cpp b/src/mesa/drivers/dri/i965/brw_scalar_visitor.cpp
index 9616b2a..d98b2cc 100644
--- a/src/mesa/drivers/dri/i965/brw_scalar_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_scalar_visitor.cpp
@@ -3255,9 +3255,9 @@ scalar_visitor::scalar_visitor(struct brw_context *brw,
struct gl_shader_program *shader_prog,
struct gl_fragment_program *fp,
unsigned dispatch_width)
- : backend_visitor(brw, shader_prog, &fp->Base, &prog_data->base,
+ : backend_visitor(brw, shader_prog, &fp->Base, &prog_data->base.base,
MESA_SHADER_FRAGMENT),
- key(key), prog_data(prog_data),
+ key(key), prog_data(&prog_data->base),
dispatch_width(dispatch_width)
{
this->fp = fp;
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index 2e3cd4b..e627fbc 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -30,6 +30,7 @@
*/
#include "brw_context.h"
+#include "brw_scalar.h"
#include "brw_wm.h"
#include "brw_state.h"
#include "main/enums.h"
@@ -123,7 +124,7 @@ brw_wm_prog_data_compare(const void *in_a, const void *in_b)
const struct brw_wm_prog_data *b = in_b;
/* Compare the base structure. */
- if (!brw_stage_prog_data_compare(&a->base, &b->base))
+ if (!brw_scalar_prog_data_compare(&a->base, &b->base))
return false;
/* Compare the rest of the structure. */
@@ -169,13 +170,13 @@ bool do_wm_prog(struct brw_context *brw,
}
/* The backend also sometimes adds params for texture size. */
param_count += 2 * ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxTextureImageUnits;
- prog_data.base.param =
+ prog_data.base.base.param =
rzalloc_array(NULL, const gl_constant_value *, param_count);
- prog_data.base.pull_param =
+ prog_data.base.base.pull_param =
rzalloc_array(NULL, const gl_constant_value *, param_count);
- prog_data.base.nr_params = param_count;
+ prog_data.base.base.nr_params = param_count;
- prog_data.barycentric_interp_modes =
+ prog_data.base.barycentric_interp_modes =
brw_compute_barycentric_interp_modes(brw, key->flat_shade,
key->persample_shading,
&fp->program);
@@ -187,9 +188,9 @@ bool do_wm_prog(struct brw_context *brw,
return false;
}
- if (prog_data.total_scratch) {
+ if (prog_data.base.total_scratch) {
brw_get_scratch_bo(brw, &brw->wm.base.scratch_bo,
- prog_data.total_scratch * brw->max_wm_threads);
+ prog_data.base.total_scratch * brw->max_wm_threads);
}
if (unlikely(INTEL_DEBUG & DEBUG_WM))
@@ -577,7 +578,7 @@ brw_upload_wm_prog(struct brw_context *brw)
(void) success;
assert(success);
}
- brw->wm.base.prog_data = &brw->wm.prog_data->base;
+ brw->wm.base.prog_data = &brw->wm.prog_data->base.base;
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h
index 77a3644..2a2dde5 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.h
+++ b/src/mesa/drivers/dri/i965/brw_wm.h
@@ -89,7 +89,7 @@ struct brw_wm_prog_key {
const unsigned *brw_wm_fs_emit(struct brw_context *brw,
void *mem_ctx,
const struct brw_wm_prog_key *key,
- struct brw_wm_prog_data *prog_data,
+ struct brw_wm_prog_data *wm_prog_data,
struct gl_fragment_program *fp,
struct gl_shader_program *prog,
unsigned *final_assembly_size);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index 84d39c1..c13e81c 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -82,18 +82,18 @@ brw_upload_wm_unit(struct brw_context *brw)
sizeof(*wm), 32, &brw->wm.base.state_offset);
memset(wm, 0, sizeof(*wm));
- if (brw->wm.prog_data->prog_offset_16) {
+ if (brw->wm.prog_data->base.prog_offset_16) {
/* These two fields should be the same pre-gen6, which is why we
* only have one hardware field to program for both dispatch
* widths.
*/
- assert(brw->wm.prog_data->base.dispatch_grf_start_reg ==
- brw->wm.prog_data->dispatch_grf_start_reg_16);
+ assert(brw->wm.prog_data->base.base.dispatch_grf_start_reg ==
+ brw->wm.prog_data->base.dispatch_grf_start_reg_16);
}
/* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_WM_PROG */
- wm->thread0.grf_reg_count = brw->wm.prog_data->reg_blocks;
- wm->wm9.grf_reg_count_2 = brw->wm.prog_data->reg_blocks_16;
+ wm->thread0.grf_reg_count = brw->wm.prog_data->base.reg_blocks;
+ wm->wm9.grf_reg_count_2 = brw->wm.prog_data->base.reg_blocks_16;
wm->thread0.kernel_start_pointer =
brw_program_reloc(brw,
@@ -107,7 +107,7 @@ brw_upload_wm_unit(struct brw_context *brw)
brw->wm.base.state_offset +
offsetof(struct brw_wm_unit_state, wm9),
brw->wm.base.prog_offset +
- brw->wm.prog_data->prog_offset_16 +
+ brw->wm.prog_data->base.prog_offset_16 +
(wm->wm9.grf_reg_count_2 << 1)) >> 6;
wm->thread1.depth_coef_urb_read_offset = 1;
@@ -122,25 +122,25 @@ brw_upload_wm_unit(struct brw_context *brw)
wm->thread1.floating_point_mode = BRW_FLOATING_POINT_IEEE_754;
wm->thread1.binding_table_entry_count =
- brw->wm.prog_data->base.binding_table.size_bytes / 4;
+ brw->wm.prog_data->base.base.binding_table.size_bytes / 4;
- if (brw->wm.prog_data->total_scratch != 0) {
+ if (brw->wm.prog_data->base.total_scratch != 0) {
wm->thread2.scratch_space_base_pointer =
brw->wm.base.scratch_bo->offset64 >> 10; /* reloc */
wm->thread2.per_thread_scratch_space =
- ffs(brw->wm.prog_data->total_scratch) - 11;
+ ffs(brw->wm.prog_data->base.total_scratch) - 11;
} else {
wm->thread2.scratch_space_base_pointer = 0;
wm->thread2.per_thread_scratch_space = 0;
}
wm->thread3.dispatch_grf_start_reg =
- brw->wm.prog_data->base.dispatch_grf_start_reg;
+ brw->wm.prog_data->base.base.dispatch_grf_start_reg;
wm->thread3.urb_entry_read_length =
- brw->wm.prog_data->num_varying_inputs * 2;
+ brw->wm.prog_data->base.num_varying_inputs * 2;
wm->thread3.urb_entry_read_offset = 0;
wm->thread3.const_urb_entry_read_length =
- brw->wm.prog_data->curb_read_length;
+ brw->wm.prog_data->base.curb_read_length;
/* BRW_NEW_CURBE_OFFSETS */
wm->thread3.const_urb_entry_read_offset = brw->curbe.wm_start * 2;
@@ -175,7 +175,7 @@ brw_upload_wm_unit(struct brw_context *brw)
wm->wm5.program_uses_killpixel = fp->UsesKill || ctx->Color.AlphaEnabled;
wm->wm5.enable_8_pix = 1;
- if (brw->wm.prog_data->prog_offset_16)
+ if (brw->wm.prog_data->base.prog_offset_16)
wm->wm5.enable_16_pix = 1;
wm->wm5.max_threads = brw->max_wm_threads - 1;
@@ -219,7 +219,7 @@ brw_upload_wm_unit(struct brw_context *brw)
wm->wm4.stats_enable = 1;
/* Emit scratch space relocation */
- if (brw->wm.prog_data->total_scratch != 0) {
+ if (brw->wm.prog_data->base.total_scratch != 0) {
drm_intel_bo_emit_reloc(brw->batch.bo,
brw->wm.base.state_offset +
offsetof(struct brw_wm_unit_state, thread2),
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 4a3111a..2eda0d9 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -484,7 +484,7 @@ brw_upload_wm_pull_constants(struct brw_context *brw)
struct brw_fragment_program *fp =
(struct brw_fragment_program *) brw->fragment_program;
/* CACHE_NEW_WM_PROG */
- struct brw_stage_prog_data *prog_data = &brw->wm.prog_data->base;
+ struct brw_stage_prog_data *prog_data = &brw->wm.prog_data->base.base;
/* _NEW_PROGRAM_CONSTANTS */
brw_upload_pull_constants(brw, BRW_NEW_SURFACES, &fp->program.Base,
@@ -536,7 +536,7 @@ brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
unsigned pitch_minus_1 = 0;
uint32_t multisampling_state = 0;
uint32_t surf_index =
- brw->wm.prog_data->binding_table.render_target_start + unit;
+ brw->wm.prog_data->base.binding_table.render_target_start + unit;
/* _NEW_BUFFERS */
const struct gl_framebuffer *fb = ctx->DrawBuffer;
@@ -621,7 +621,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
/* _NEW_BUFFERS */
mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
uint32_t surf_index =
- brw->wm.prog_data->binding_table.render_target_start + unit;
+ brw->wm.prog_data->base.binding_table.render_target_start + unit;
assert(!layered);
@@ -884,7 +884,7 @@ brw_upload_wm_ubo_surfaces(struct brw_context *brw)
/* CACHE_NEW_WM_PROG */
brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_FRAGMENT],
- &brw->wm.base, &brw->wm.prog_data->base);
+ &brw->wm.base, &brw->wm.prog_data->base.base);
}
const struct brw_tracked_state brw_wm_ubo_surfaces = {
@@ -933,7 +933,7 @@ brw_upload_wm_abo_surfaces(struct brw_context *brw)
if (prog) {
/* CACHE_NEW_WM_PROG */
brw_upload_abo_surfaces(brw, prog, &brw->wm.base,
- &brw->wm.prog_data->base);
+ &brw->wm.prog_data->base.base);
}
}
diff --git a/src/mesa/drivers/dri/i965/gen6_clip_state.c b/src/mesa/drivers/dri/i965/gen6_clip_state.c
index e8c1b91..b8f16fb 100644
--- a/src/mesa/drivers/dri/i965/gen6_clip_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_clip_state.c
@@ -44,7 +44,7 @@ upload_clip_state(struct brw_context *brw)
struct gl_framebuffer *fb = ctx->DrawBuffer;
/* CACHE_NEW_WM_PROG */
- if (brw->wm.prog_data->barycentric_interp_modes &
+ if (brw->wm.prog_data->base.barycentric_interp_modes &
BRW_WM_NONPERSPECTIVE_BARYCENTRIC_BITS) {
dw2 |= GEN6_CLIP_NON_PERSPECTIVE_BARYCENTRIC_ENABLE;
}
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index 843507e..e7620a2 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -159,7 +159,7 @@ calculate_attr_overrides(const struct brw_context *brw,
brw->fragment_program->InterpQualifier[attr];
bool is_gl_Color = attr == VARYING_SLOT_COL0 || attr == VARYING_SLOT_COL1;
/* CACHE_NEW_WM_PROG */
- int input_index = brw->wm.prog_data->urb_setup[attr];
+ int input_index = brw->wm.prog_data->base.urb_setup[attr];
if (input_index < 0)
continue;
@@ -226,7 +226,7 @@ upload_sf_state(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
/* CACHE_NEW_WM_PROG */
- uint32_t num_outputs = brw->wm.prog_data->num_varying_inputs;
+ uint32_t num_outputs = brw->wm.prog_data->base.num_varying_inputs;
uint32_t dw1, dw2, dw3, dw4;
uint32_t point_sprite_enables;
uint32_t flat_enables;
diff --git a/src/mesa/drivers/dri/i965/gen6_surface_state.c b/src/mesa/drivers/dri/i965/gen6_surface_state.c
index 27b4419..5a00832 100644
--- a/src/mesa/drivers/dri/i965/gen6_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_surface_state.c
@@ -64,7 +64,7 @@ gen6_update_renderbuffer_surface(struct brw_context *brw,
rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
uint32_t surf_index =
- brw->wm.prog_data->binding_table.render_target_start + unit;
+ brw->wm.prog_data->base.binding_table.render_target_start + unit;
intel_miptree_used_for_rendering(irb->mt);
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index de95db8..1762d30 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -84,7 +84,7 @@ upload_wm_state(struct brw_context *brw)
*
* "[DevSNB]: This packet must be followed by WM_STATE."
*/
- if (brw->wm.prog_data->base.nr_params == 0) {
+ if (brw->wm.prog_data->base.base.nr_params == 0) {
/* Disable the push constant buffers. */
BEGIN_BATCH(5);
OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (5 - 2));
@@ -126,7 +126,7 @@ upload_wm_state(struct brw_context *brw)
GEN6_WM_SAMPLER_COUNT_SHIFT;
/* CACHE_NEW_WM_PROG */
- dw2 |= ((brw->wm.prog_data->base.binding_table.size_bytes / 4) <<
+ dw2 |= ((brw->wm.prog_data->base.base.binding_table.size_bytes / 4) <<
GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT);
dw5 |= (brw->max_wm_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT;
@@ -142,32 +142,32 @@ upload_wm_state(struct brw_context *brw)
_mesa_get_min_invocations_per_fragment(ctx, brw->fragment_program, false);
assert(min_inv_per_frag >= 1);
- if (brw->wm.prog_data->prog_offset_16) {
+ if (brw->wm.prog_data->base.prog_offset_16) {
dw5 |= GEN6_WM_16_DISPATCH_ENABLE;
if (min_inv_per_frag == 1) {
dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
- dw4 |= (brw->wm.prog_data->base.dispatch_grf_start_reg <<
+ dw4 |= (brw->wm.prog_data->base.base.dispatch_grf_start_reg <<
GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
- dw4 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 <<
+ dw4 |= (brw->wm.prog_data->base.dispatch_grf_start_reg_16 <<
GEN6_WM_DISPATCH_START_GRF_SHIFT_2);
ksp0 = brw->wm.base.prog_offset;
- ksp2 = brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16;
+ ksp2 = brw->wm.base.prog_offset + brw->wm.prog_data->base.prog_offset_16;
} else {
- dw4 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 <<
+ dw4 |= (brw->wm.prog_data->base.dispatch_grf_start_reg_16 <<
GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
- ksp0 = brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16;
+ ksp0 = brw->wm.base.prog_offset + brw->wm.prog_data->base.prog_offset_16;
}
}
else {
dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
- dw4 |= (brw->wm.prog_data->base.dispatch_grf_start_reg <<
+ dw4 |= (brw->wm.prog_data->base.base.dispatch_grf_start_reg <<
GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
ksp0 = brw->wm.base.prog_offset;
}
/* CACHE_NEW_WM_PROG | _NEW_COLOR */
- if (brw->wm.prog_data->dual_src_blend &&
+ if (brw->wm.prog_data->base.dual_src_blend &&
(ctx->Color.BlendEnabled & 1) &&
ctx->Color.Blend[0]._UsesDualSrc) {
dw5 |= GEN6_WM_DUAL_SOURCE_BLEND_ENABLE;
@@ -187,13 +187,13 @@ upload_wm_state(struct brw_context *brw)
if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
dw5 |= GEN6_WM_COMPUTED_DEPTH;
/* CACHE_NEW_WM_PROG */
- dw6 |= brw->wm.prog_data->barycentric_interp_modes <<
+ dw6 |= brw->wm.prog_data->base.barycentric_interp_modes <<
GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
/* _NEW_COLOR, _NEW_MULTISAMPLE */
if (fp->program.UsesKill || ctx->Color.AlphaEnabled ||
ctx->Multisample.SampleAlphaToCoverage ||
- brw->wm.prog_data->uses_omask)
+ brw->wm.prog_data->base.uses_omask)
dw5 |= GEN6_WM_KILL_ENABLE;
/* _NEW_BUFFERS | _NEW_COLOR */
@@ -209,11 +209,11 @@ upload_wm_state(struct brw_context *brw)
* Target Write messages. If present, the oMask data is used to mask off
* samples."
*/
- if(brw->wm.prog_data->uses_omask)
+ if(brw->wm.prog_data->base.uses_omask)
dw5 |= GEN6_WM_OMASK_TO_RENDER_TARGET;
/* CACHE_NEW_WM_PROG */
- dw6 |= brw->wm.prog_data->num_varying_inputs <<
+ dw6 |= brw->wm.prog_data->base.num_varying_inputs <<
GEN6_WM_NUM_SF_OUTPUTS_SHIFT;
if (multisampled_fbo) {
/* _NEW_MULTISAMPLE */
@@ -275,7 +275,7 @@ upload_wm_state(struct brw_context *brw)
* We only require XY sample offsets. So, this recommendation doesn't
* look useful at the moment. We might need this in future.
*/
- if (brw->wm.prog_data->uses_pos_offset)
+ if (brw->wm.prog_data->base.uses_pos_offset)
dw6 |= GEN6_WM_POSOFFSET_SAMPLE;
else
dw6 |= GEN6_WM_POSOFFSET_NONE;
@@ -284,10 +284,10 @@ upload_wm_state(struct brw_context *brw)
OUT_BATCH(_3DSTATE_WM << 16 | (9 - 2));
OUT_BATCH(ksp0);
OUT_BATCH(dw2);
- if (brw->wm.prog_data->total_scratch) {
+ if (brw->wm.prog_data->base.total_scratch) {
OUT_RELOC(brw->wm.base.scratch_bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- ffs(brw->wm.prog_data->total_scratch) - 11);
+ ffs(brw->wm.prog_data->base.total_scratch) - 11);
} else {
OUT_BATCH(0);
}
diff --git a/src/mesa/drivers/dri/i965/gen7_sf_state.c b/src/mesa/drivers/dri/i965/gen7_sf_state.c
index 4badc82..111229b 100644
--- a/src/mesa/drivers/dri/i965/gen7_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sf_state.c
@@ -34,7 +34,7 @@ upload_sbe_state(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
/* CACHE_NEW_WM_PROG */
- uint32_t num_outputs = brw->wm.prog_data->num_varying_inputs;
+ uint32_t num_outputs = brw->wm.prog_data->base.num_varying_inputs;
uint32_t dw1;
uint32_t point_sprite_enables;
uint32_t flat_enables;
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 278cf17..f93fb43 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -79,7 +79,7 @@ upload_wm_state(struct brw_context *brw)
}
}
/* CACHE_NEW_WM_PROG */
- dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
+ dw1 |= brw->wm.prog_data->base.barycentric_interp_modes <<
GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
/* _NEW_COLOR, _NEW_MULTISAMPLE */
@@ -87,7 +87,7 @@ upload_wm_state(struct brw_context *brw)
*/
if (fp->program.UsesKill || ctx->Color.AlphaEnabled ||
ctx->Multisample.SampleAlphaToCoverage ||
- brw->wm.prog_data->uses_omask) {
+ brw->wm.prog_data->base.uses_omask) {
dw1 |= GEN7_WM_KILL_ENABLE;
}
@@ -149,7 +149,7 @@ upload_ps_state(struct brw_context *brw)
(ALIGN(brw->wm.base.sampler_count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
/* CACHE_NEW_WM_PROG */
- dw2 |= ((brw->wm.prog_data->base.binding_table.size_bytes / 4) <<
+ dw2 |= ((brw->wm.prog_data->base.base.binding_table.size_bytes / 4) <<
GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
/* Use ALT floating point mode for ARB fragment programs, because they
@@ -170,7 +170,7 @@ upload_ps_state(struct brw_context *brw)
dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
/* CACHE_NEW_WM_PROG */
- if (brw->wm.prog_data->base.nr_params > 0)
+ if (brw->wm.prog_data->base.base.nr_params > 0)
dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
/* From the IVB PRM, volume 2 part 1, page 287:
@@ -180,7 +180,7 @@ upload_ps_state(struct brw_context *brw)
* Target Write messages. If present, the oMask data is used to mask off
* samples."
*/
- if (brw->wm.prog_data->uses_omask)
+ if (brw->wm.prog_data->base.uses_omask)
dw4 |= GEN7_PS_OMASK_TO_RENDER_TARGET;
/* From the IVB PRM, volume 2 part 1, page 287:
@@ -194,7 +194,7 @@ upload_ps_state(struct brw_context *brw)
* We only require XY sample offsets. So, this recommendation doesn't
* look useful at the moment. We might need this in future.
*/
- if (brw->wm.prog_data->uses_pos_offset)
+ if (brw->wm.prog_data->base.uses_pos_offset)
dw4 |= GEN7_PS_POSOFFSET_SAMPLE;
else
dw4 |= GEN7_PS_POSOFFSET_NONE;
@@ -204,14 +204,14 @@ upload_ps_state(struct brw_context *brw)
* The hardware wedges if you have this bit set but don't turn on any dual
* source blend factors.
*/
- if (brw->wm.prog_data->dual_src_blend &&
+ if (brw->wm.prog_data->base.dual_src_blend &&
(ctx->Color.BlendEnabled & 1) &&
ctx->Color.Blend[0]._UsesDualSrc) {
dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE;
}
/* CACHE_NEW_WM_PROG */
- if (brw->wm.prog_data->num_varying_inputs != 0)
+ if (brw->wm.prog_data->base.num_varying_inputs != 0)
dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
/* In case of non 1x per sample shading, only one of SIMD8 and SIMD16
@@ -223,25 +223,25 @@ upload_ps_state(struct brw_context *brw)
_mesa_get_min_invocations_per_fragment(ctx, brw->fragment_program, false);
assert(min_inv_per_frag >= 1);
- if (brw->wm.prog_data->prog_offset_16 || brw->wm.prog_data->no_8) {
+ if (brw->wm.prog_data->base.prog_offset_16 || brw->wm.prog_data->base.no_8) {
dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
- if (!brw->wm.prog_data->no_8 && min_inv_per_frag == 1) {
+ if (!brw->wm.prog_data->base.no_8 && min_inv_per_frag == 1) {
dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
- dw5 |= (brw->wm.prog_data->base.dispatch_grf_start_reg <<
+ dw5 |= (brw->wm.prog_data->base.base.dispatch_grf_start_reg <<
GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
- dw5 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 <<
+ dw5 |= (brw->wm.prog_data->base.dispatch_grf_start_reg_16 <<
GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
ksp0 = brw->wm.base.prog_offset;
- ksp2 = brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16;
+ ksp2 = brw->wm.base.prog_offset + brw->wm.prog_data->base.prog_offset_16;
} else {
- dw5 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 <<
+ dw5 |= (brw->wm.prog_data->base.dispatch_grf_start_reg_16 <<
GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
- ksp0 = brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16;
+ ksp0 = brw->wm.base.prog_offset + brw->wm.prog_data->base.prog_offset_16;
}
}
else {
dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
- dw5 |= (brw->wm.prog_data->base.dispatch_grf_start_reg <<
+ dw5 |= (brw->wm.prog_data->base.base.dispatch_grf_start_reg <<
GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
ksp0 = brw->wm.base.prog_offset;
}
@@ -252,10 +252,10 @@ upload_ps_state(struct brw_context *brw)
OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
OUT_BATCH(ksp0);
OUT_BATCH(dw2);
- if (brw->wm.prog_data->total_scratch) {
+ if (brw->wm.prog_data->base.total_scratch) {
OUT_RELOC(brw->wm.base.scratch_bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- ffs(brw->wm.prog_data->total_scratch) - 11);
+ ffs(brw->wm.prog_data->base.total_scratch) - 11);
} else {
OUT_BATCH(0);
}
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index c257cb7..bca7c2d 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -424,7 +424,7 @@ gen7_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit)
/* _NEW_BUFFERS */
const struct gl_framebuffer *fb = ctx->DrawBuffer;
uint32_t surf_index =
- brw->wm.prog_data->binding_table.render_target_start + unit;
+ brw->wm.prog_data->base.binding_table.render_target_start + unit;
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32,
&brw->wm.base.surf_offset[surf_index]);
@@ -472,7 +472,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
uint32_t surf_index =
- brw->wm.prog_data->binding_table.render_target_start + unit;
+ brw->wm.prog_data->base.binding_table.render_target_start + unit;
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32,
&brw->wm.base.surf_offset[surf_index]);
diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c b/src/mesa/drivers/dri/i965/gen8_ps_state.c
index 5e313bf..f6e9d39 100644
--- a/src/mesa/drivers/dri/i965/gen8_ps_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c
@@ -42,7 +42,7 @@ upload_ps_extra(struct brw_context *brw)
dw1 |= GEN8_PSX_KILL_ENABLE;
/* BRW_NEW_FRAGMENT_PROGRAM */
- if (brw->wm.prog_data->num_varying_inputs != 0)
+ if (brw->wm.prog_data->base.num_varying_inputs != 0)
dw1 |= GEN8_PSX_ATTRIBUTE_ENABLE;
if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
@@ -74,7 +74,7 @@ upload_ps_extra(struct brw_context *brw)
if (fp->program.Base.SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN)
dw1 |= GEN8_PSX_SHADER_USES_INPUT_COVERAGE_MASK;
- if (brw->wm.prog_data->uses_omask)
+ if (brw->wm.prog_data->base.uses_omask)
dw1 |= GEN8_PSX_OMASK_TO_RENDER_TARGET;
BEGIN_BATCH(2);
@@ -112,7 +112,7 @@ upload_wm_state(struct brw_context *brw)
dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
/* CACHE_NEW_WM_PROG */
- dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
+ dw1 |= brw->wm.prog_data->base.barycentric_interp_modes <<
GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
BEGIN_BATCH(2);
@@ -147,7 +147,7 @@ upload_ps_state(struct brw_context *brw)
/* CACHE_NEW_WM_PROG */
dw3 |=
- ((brw->wm.prog_data->base.binding_table.size_bytes / 4) <<
+ ((brw->wm.prog_data->base.base.binding_table.size_bytes / 4) <<
GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
/* Use ALT floating point mode for ARB fragment programs, because they
@@ -164,7 +164,7 @@ upload_ps_state(struct brw_context *brw)
dw6 |= (64 - 2) << HSW_PS_MAX_THREADS_SHIFT;
/* CACHE_NEW_WM_PROG */
- if (brw->wm.prog_data->base.nr_params > 0)
+ if (brw->wm.prog_data->base.base.nr_params > 0)
dw6 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
/* From the documentation for this packet:
@@ -180,7 +180,7 @@ upload_ps_state(struct brw_context *brw)
* We only require XY sample offsets. So, this recommendation doesn't
* look useful at the moment. We might need this in future.
*/
- if (brw->wm.prog_data->uses_pos_offset)
+ if (brw->wm.prog_data->base.uses_pos_offset)
dw6 |= GEN7_PS_POSOFFSET_SAMPLE;
else
dw6 |= GEN7_PS_POSOFFSET_NONE;
@@ -197,25 +197,25 @@ upload_ps_state(struct brw_context *brw)
_mesa_get_min_invocations_per_fragment(ctx, brw->fragment_program, false);
assert(min_invocations_per_fragment >= 1);
- if (brw->wm.prog_data->prog_offset_16 || brw->wm.prog_data->no_8) {
+ if (brw->wm.prog_data->base.prog_offset_16 || brw->wm.prog_data->base.no_8) {
dw6 |= GEN7_PS_16_DISPATCH_ENABLE;
- if (!brw->wm.prog_data->no_8 && min_invocations_per_fragment == 1) {
+ if (!brw->wm.prog_data->base.no_8 && min_invocations_per_fragment == 1) {
dw6 |= GEN7_PS_8_DISPATCH_ENABLE;
- dw7 |= (brw->wm.prog_data->base.dispatch_grf_start_reg <<
+ dw7 |= (brw->wm.prog_data->base.base.dispatch_grf_start_reg <<
GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
- dw7 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 <<
+ dw7 |= (brw->wm.prog_data->base.dispatch_grf_start_reg_16 <<
GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
ksp0 = brw->wm.base.prog_offset;
- ksp2 = brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16;
+ ksp2 = brw->wm.base.prog_offset + brw->wm.prog_data->base.prog_offset_16;
} else {
- dw7 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 <<
+ dw7 |= (brw->wm.prog_data->base.dispatch_grf_start_reg_16 <<
GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
- ksp0 = brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16;
+ ksp0 = brw->wm.base.prog_offset + brw->wm.prog_data->base.prog_offset_16;
}
} else {
dw6 |= GEN7_PS_8_DISPATCH_ENABLE;
- dw7 |= (brw->wm.prog_data->base.dispatch_grf_start_reg <<
+ dw7 |= (brw->wm.prog_data->base.base.dispatch_grf_start_reg <<
GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
ksp0 = brw->wm.base.prog_offset;
}
@@ -225,10 +225,10 @@ upload_ps_state(struct brw_context *brw)
OUT_BATCH(ksp0);
OUT_BATCH(0);
OUT_BATCH(dw3);
- if (brw->wm.prog_data->total_scratch) {
+ if (brw->wm.prog_data->base.total_scratch) {
OUT_RELOC64(brw->wm.base.scratch_bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- ffs(brw->wm.prog_data->total_scratch) - 11);
+ ffs(brw->wm.prog_data->base.total_scratch) - 11);
} else {
OUT_BATCH(0);
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/gen8_sf_state.c b/src/mesa/drivers/dri/i965/gen8_sf_state.c
index 4263eaf..ebdd272 100644
--- a/src/mesa/drivers/dri/i965/gen8_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_sf_state.c
@@ -34,7 +34,7 @@ upload_sbe(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
/* CACHE_NEW_WM_PROG */
- uint32_t num_outputs = brw->wm.prog_data->num_varying_inputs;
+ uint32_t num_outputs = brw->wm.prog_data->base.num_varying_inputs;
uint16_t attr_overrides[VARYING_SLOT_MAX];
uint32_t urb_entry_read_length;
uint32_t point_sprite_enables;
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 40eb2ea..efa006e 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -281,7 +281,7 @@ gen8_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit)
/* _NEW_BUFFERS */
const struct gl_framebuffer *fb = ctx->DrawBuffer;
uint32_t surf_index =
- brw->wm.prog_data->binding_table.render_target_start + unit;
+ brw->wm.prog_data->base.binding_table.render_target_start + unit;
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 13 * 4, 64,
&brw->wm.base.surf_offset[surf_index]);
@@ -324,7 +324,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
uint32_t surf_index =
- brw->wm.prog_data->binding_table.render_target_start + unit;
+ brw->wm.prog_data->base.binding_table.render_target_start + unit;
intel_miptree_used_for_rendering(mt);
--
2.1.0
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