[Mesa-dev] [PATCH 02/10] i965/fs: Add a width field to fs_inst
Jason Ekstrand
jason at jlekstrand.net
Thu Sep 4 22:19:06 PDT 2014
This will, eventually, allow us to manage execution widths of instructions
in a much more natural way from the fs_visitor level.
Signed-off-by: Jason Ekstrand <jason.ekstrand at intel.com>
---
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 10 +--
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h | 32 +++++-----
src/mesa/drivers/dri/i965/brw_fs.cpp | 76 +++++++++++++----------
src/mesa/drivers/dri/i965/brw_fs.h | 30 ++++++---
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 4 +-
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 2 +-
6 files changed, 89 insertions(+), 65 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
index 82ece73..31f4a20 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
@@ -69,7 +69,7 @@ brw_blorp_eu_emitter::emit_kill_if_outside_rect(const struct brw_reg &x,
emit_cmp(BRW_CONDITIONAL_L, x, dst_x1)->predicate = BRW_PREDICATE_NORMAL;
emit_cmp(BRW_CONDITIONAL_L, y, dst_y1)->predicate = BRW_PREDICATE_NORMAL;
- fs_inst *inst = new (mem_ctx) fs_inst(BRW_OPCODE_AND, g1, f0, g1);
+ fs_inst *inst = new (mem_ctx) fs_inst(BRW_OPCODE_AND, 16, g1, f0, g1);
inst->force_writemask_all = true;
insts.push_tail(inst);
}
@@ -80,7 +80,7 @@ brw_blorp_eu_emitter::emit_texture_lookup(const struct brw_reg &dst,
unsigned base_mrf,
unsigned msg_length)
{
- fs_inst *inst = new (mem_ctx) fs_inst(op, dst, brw_message_reg(base_mrf),
+ fs_inst *inst = new (mem_ctx) fs_inst(op, 16, dst, brw_message_reg(base_mrf),
fs_reg(0u));
inst->base_mrf = base_mrf;
@@ -96,7 +96,7 @@ brw_blorp_eu_emitter::emit_render_target_write(const struct brw_reg &src0,
unsigned msg_length,
bool use_header)
{
- fs_inst *inst = new (mem_ctx) fs_inst(FS_OPCODE_BLORP_FB_WRITE);
+ fs_inst *inst = new (mem_ctx) fs_inst(FS_OPCODE_BLORP_FB_WRITE, 16);
inst->src[0] = src0;
inst->base_mrf = msg_reg_nr;
@@ -115,7 +115,7 @@ brw_blorp_eu_emitter::emit_combine(enum opcode combine_opcode,
{
assert(combine_opcode == BRW_OPCODE_ADD || combine_opcode == BRW_OPCODE_AVG);
- insts.push_tail(new (mem_ctx) fs_inst(combine_opcode, dst, src_1, src_2));
+ insts.push_tail(new (mem_ctx) fs_inst(combine_opcode, 16, dst, src_1, src_2));
}
fs_inst *
@@ -123,7 +123,7 @@ brw_blorp_eu_emitter::emit_cmp(enum brw_conditional_mod op,
const struct brw_reg &x,
const struct brw_reg &y)
{
- fs_inst *cmp = new (mem_ctx) fs_inst(BRW_OPCODE_CMP,
+ fs_inst *cmp = new (mem_ctx) fs_inst(BRW_OPCODE_CMP, 16,
vec16(brw_null_reg()), x, y);
cmp->conditional_mod = op;
insts.push_tail(cmp);
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
index 0459a7e..cd50da4 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
@@ -65,7 +65,7 @@ protected:
{
emit_cmp(op, x, y);
- fs_inst *mv = new (mem_ctx) fs_inst(BRW_OPCODE_MOV, dst, src);
+ fs_inst *mv = new (mem_ctx) fs_inst(BRW_OPCODE_MOV, 16, dst, src);
mv->predicate = BRW_PREDICATE_NORMAL;
insts.push_tail(mv);
}
@@ -82,17 +82,17 @@ protected:
const struct brw_reg &src3)
{
insts.push_tail(
- new (mem_ctx) fs_inst(BRW_OPCODE_LRP, dst, src1, src2, src3));
+ new (mem_ctx) fs_inst(BRW_OPCODE_LRP, 16, dst, src1, src2, src3));
}
inline void emit_mov(const struct brw_reg& dst, const struct brw_reg& src)
{
- insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_MOV, dst, src));
+ insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_MOV, 16, dst, src));
}
inline void emit_mov_8(const struct brw_reg& dst, const struct brw_reg& src)
{
- fs_inst *mv = new (mem_ctx) fs_inst(BRW_OPCODE_MOV, dst, src);
+ fs_inst *mv = new (mem_ctx) fs_inst(BRW_OPCODE_MOV, 8, dst, src);
mv->force_uncompressed = true;
insts.push_tail(mv);
}
@@ -101,21 +101,21 @@ protected:
const struct brw_reg& src1,
const struct brw_reg& src2)
{
- insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_AND, dst, src1, src2));
+ insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_AND, 16, dst, src1, src2));
}
inline void emit_add(const struct brw_reg& dst,
const struct brw_reg& src1,
const struct brw_reg& src2)
{
- insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_ADD, dst, src1, src2));
+ insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_ADD, 16, dst, src1, src2));
}
inline void emit_add_8(const struct brw_reg& dst,
const struct brw_reg& src1,
const struct brw_reg& src2)
{
- fs_inst *add = new (mem_ctx) fs_inst(BRW_OPCODE_ADD, dst, src1, src2);
+ fs_inst *add = new (mem_ctx) fs_inst(BRW_OPCODE_ADD, 8, dst, src1, src2);
add->force_uncompressed = true;
insts.push_tail(add);
}
@@ -124,40 +124,40 @@ protected:
const struct brw_reg& src1,
const struct brw_reg& src2)
{
- insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_MUL, dst, src1, src2));
+ insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_MUL, 16, dst, src1, src2));
}
inline void emit_shr(const struct brw_reg& dst,
const struct brw_reg& src1,
const struct brw_reg& src2)
{
- insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_SHR, dst, src1, src2));
+ insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_SHR, 16, dst, src1, src2));
}
inline void emit_shl(const struct brw_reg& dst,
const struct brw_reg& src1,
const struct brw_reg& src2)
{
- insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_SHL, dst, src1, src2));
+ insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_SHL, 16, dst, src1, src2));
}
inline void emit_or(const struct brw_reg& dst,
const struct brw_reg& src1,
const struct brw_reg& src2)
{
- insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_OR, dst, src1, src2));
+ insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_OR, 16, dst, src1, src2));
}
inline void emit_frc(const struct brw_reg& dst,
const struct brw_reg& src)
{
- insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_FRC, dst, src));
+ insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_FRC, 16, dst, src));
}
inline void emit_rndd(const struct brw_reg& dst,
const struct brw_reg& src)
{
- insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_RNDD, dst, src));
+ insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_RNDD, 16, dst, src));
}
inline void emit_cmp_if(enum brw_conditional_mod op,
@@ -165,17 +165,17 @@ protected:
const struct brw_reg &y)
{
emit_cmp(op, x, y);
- insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_IF));
+ insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_IF, 16));
}
inline void emit_else(void)
{
- insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_ELSE));
+ insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_ELSE, 16));
}
inline void emit_endif(void)
{
- insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_ENDIF));
+ insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_ENDIF, 16));
}
private:
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index ab11a79..c39a062 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -53,7 +53,8 @@ extern "C" {
#include "glsl/glsl_types.h"
void
-fs_inst::init(enum opcode opcode, const fs_reg &dst, fs_reg *src, int sources)
+fs_inst::init(enum opcode opcode, uint8_t exec_width, const fs_reg &dst,
+ fs_reg *src, int sources)
{
memset(this, 0, sizeof(*this));
@@ -61,6 +62,7 @@ fs_inst::init(enum opcode opcode, const fs_reg &dst, fs_reg *src, int sources)
this->dst = dst;
this->src = src;
this->sources = sources;
+ this->width = exec_width;
this->conditional_mod = BRW_CONDITIONAL_NONE;
@@ -70,41 +72,49 @@ fs_inst::init(enum opcode opcode, const fs_reg &dst, fs_reg *src, int sources)
this->writes_accumulator = false;
}
-fs_inst::fs_inst(enum opcode opcode, const fs_reg &dst)
+fs_inst::fs_inst()
{
fs_reg *src = ralloc_array(this, fs_reg, 3);
- init(opcode, dst, src, 0);
+ init(BRW_OPCODE_NOP, 8, dst, src, 0);
}
-fs_inst::fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0)
+fs_inst::fs_inst(enum opcode opcode, uint8_t exec_width, const fs_reg &dst)
+{
+ fs_reg *src = ralloc_array(this, fs_reg, 3);
+ init(opcode, exec_width, dst, src, 0);
+}
+
+fs_inst::fs_inst(enum opcode opcode, uint8_t exec_width, const fs_reg &dst,
+ const fs_reg &src0)
{
fs_reg *src = ralloc_array(this, fs_reg, 3);
src[0] = src0;
- init(opcode, dst, src, 1);
+ init(opcode, exec_width, dst, src, 1);
}
-fs_inst::fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
- const fs_reg &src1)
+fs_inst::fs_inst(enum opcode opcode, uint8_t exec_width, const fs_reg &dst,
+ const fs_reg &src0, const fs_reg &src1)
{
fs_reg *src = ralloc_array(this, fs_reg, 3);
src[0] = src0;
src[1] = src1;
- init(opcode, dst, src, 2);
+ init(opcode, exec_width, dst, src, 2);
}
-fs_inst::fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
- const fs_reg &src1, const fs_reg &src2)
+fs_inst::fs_inst(enum opcode opcode, uint8_t exec_width, const fs_reg &dst,
+ const fs_reg &src0, const fs_reg &src1, const fs_reg &src2)
{
fs_reg *src = ralloc_array(this, fs_reg, 3);
src[0] = src0;
src[1] = src1;
src[2] = src2;
- init(opcode, dst, src, 3);
+ init(opcode, exec_width, dst, src, 3);
}
-fs_inst::fs_inst(enum opcode opcode, const fs_reg &dst, fs_reg src[], int sources)
+fs_inst::fs_inst(enum opcode opcode, uint8_t exec_width, const fs_reg &dst,
+ fs_reg src[], int sources)
{
- init(opcode, dst, src, sources);
+ init(opcode, exec_width, dst, src, sources);
}
fs_inst::fs_inst(const fs_inst &that)
@@ -130,7 +140,7 @@ fs_inst::resize_sources(uint8_t num_sources)
fs_inst * \
fs_visitor::op(const fs_reg &dst, const fs_reg &src0) \
{ \
- return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0); \
+ return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dispatch_width, dst, src0); \
}
#define ALU2(op) \
@@ -138,7 +148,7 @@ fs_inst::resize_sources(uint8_t num_sources)
fs_visitor::op(const fs_reg &dst, const fs_reg &src0, \
const fs_reg &src1) \
{ \
- return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1); \
+ return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dispatch_width, dst, src0, src1); \
}
#define ALU2_ACC(op) \
@@ -146,7 +156,7 @@ fs_inst::resize_sources(uint8_t num_sources)
fs_visitor::op(const fs_reg &dst, const fs_reg &src0, \
const fs_reg &src1) \
{ \
- fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1);\
+ fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_##op, dispatch_width, dst, src0, src1);\
inst->writes_accumulator = true; \
return inst; \
}
@@ -156,7 +166,7 @@ fs_inst::resize_sources(uint8_t num_sources)
fs_visitor::op(const fs_reg &dst, const fs_reg &src0, \
const fs_reg &src1, const fs_reg &src2) \
{ \
- return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1, src2);\
+ return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dispatch_width, dst, src0, src1, src2);\
}
ALU1(NOT)
@@ -192,7 +202,7 @@ ALU2(MAC)
fs_inst *
fs_visitor::IF(enum brw_predicate predicate)
{
- fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_IF);
+ fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_IF, dispatch_width);
inst->predicate = predicate;
return inst;
}
@@ -203,7 +213,7 @@ fs_visitor::IF(const fs_reg &src0, const fs_reg &src1,
enum brw_conditional_mod condition)
{
assert(brw->gen == 6);
- fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_IF,
+ fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_IF, dispatch_width,
reg_null_d, src0, src1);
inst->conditional_mod = condition;
return inst;
@@ -241,7 +251,7 @@ fs_visitor::CMP(fs_reg dst, fs_reg src0, fs_reg src1,
resolve_ud_negate(&src0);
resolve_ud_negate(&src1);
- inst = new(mem_ctx) fs_inst(BRW_OPCODE_CMP, dst, src0, src1);
+ inst = new(mem_ctx) fs_inst(BRW_OPCODE_CMP, dispatch_width, dst, src0, src1);
inst->conditional_mod = condition;
return inst;
@@ -250,8 +260,8 @@ fs_visitor::CMP(fs_reg dst, fs_reg src0, fs_reg src1,
fs_inst *
fs_visitor::LOAD_PAYLOAD(const fs_reg &dst, fs_reg *src, int sources)
{
- fs_inst *inst = new(mem_ctx) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD, dst, src,
- sources);
+ fs_inst *inst = new(mem_ctx) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD,
+ dispatch_width, dst, src, sources);
inst->regs_written = sources;
return inst;
@@ -297,7 +307,8 @@ fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_reg &dst,
else
op = FS_OPCODE_VARYING_PULL_CONSTANT_LOAD;
fs_reg vec4_result = fs_reg(GRF, virtual_grf_alloc(4 * scale), dst.type);
- inst = new(mem_ctx) fs_inst(op, vec4_result, surf_index, vec4_offset);
+ inst = new(mem_ctx) fs_inst(op, dispatch_width,
+ vec4_result, surf_index, vec4_offset);
inst->regs_written = 4 * scale;
instructions.push_tail(inst);
@@ -353,6 +364,7 @@ fs_inst::equals(fs_inst *inst) const
eot == inst->eot &&
header_present == inst->header_present &&
shadow_compare == inst->shadow_compare &&
+ width == inst->width &&
offset == inst->offset);
}
@@ -631,7 +643,7 @@ fs_visitor::emit_shader_time_write(enum shader_time_shader_type type,
else
payload = fs_reg(this, glsl_type::uint_type);
- emit(new(mem_ctx) fs_inst(SHADER_OPCODE_SHADER_TIME_ADD,
+ emit(new(mem_ctx) fs_inst(SHADER_OPCODE_SHADER_TIME_ADD, dispatch_width,
fs_reg(), payload, offset, value));
}
@@ -700,40 +712,40 @@ fs_visitor::no16(const char *format, ...)
fs_inst *
fs_visitor::emit(enum opcode opcode)
{
- return emit(new(mem_ctx) fs_inst(opcode));
+ return emit(new(mem_ctx) fs_inst(opcode, dispatch_width));
}
fs_inst *
fs_visitor::emit(enum opcode opcode, const fs_reg &dst)
{
- return emit(new(mem_ctx) fs_inst(opcode, dst));
+ return emit(new(mem_ctx) fs_inst(opcode, dispatch_width, dst));
}
fs_inst *
fs_visitor::emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0)
{
- return emit(new(mem_ctx) fs_inst(opcode, dst, src0));
+ return emit(new(mem_ctx) fs_inst(opcode, dispatch_width, dst, src0));
}
fs_inst *
fs_visitor::emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
const fs_reg &src1)
{
- return emit(new(mem_ctx) fs_inst(opcode, dst, src0, src1));
+ return emit(new(mem_ctx) fs_inst(opcode, dispatch_width, dst, src0, src1));
}
fs_inst *
fs_visitor::emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
const fs_reg &src1, const fs_reg &src2)
{
- return emit(new(mem_ctx) fs_inst(opcode, dst, src0, src1, src2));
+ return emit(new(mem_ctx) fs_inst(opcode, dispatch_width, dst, src0, src1, src2));
}
fs_inst *
fs_visitor::emit(enum opcode opcode, const fs_reg &dst,
fs_reg src[], int sources)
{
- return emit(new(mem_ctx) fs_inst(opcode, dst, src, sources));
+ return emit(new(mem_ctx) fs_inst(opcode, dispatch_width, dst, src, sources));
}
void
@@ -1953,7 +1965,7 @@ fs_visitor::demote_pull_constants()
} else {
fs_reg offset = fs_reg((unsigned)(pull_index * 4) & ~15);
fs_inst *pull =
- new(mem_ctx) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
+ new(mem_ctx) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD, 8,
dst, surf_index, offset);
inst->insert_before(block, pull);
inst->src[i].set_smear(pull_index & 3);
@@ -2722,7 +2734,7 @@ fs_visitor::lower_uniform_pull_constant_loads()
* by live variable analysis, or register allocation will explode.
*/
fs_inst *setup = new(mem_ctx) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET,
- payload, const_offset_reg);
+ 8, payload, const_offset_reg);
setup->force_writemask_all = true;
setup->ir = inst->ir;
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index 506f3ad..1f28e04 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -153,18 +153,23 @@ public:
class fs_inst : public backend_instruction {
fs_inst &operator=(const fs_inst &);
+ void init(enum opcode opcode, uint8_t exec_width, const fs_reg &dst,
+ fs_reg *src, int sources);
+
public:
DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
- void init(enum opcode opcode, const fs_reg &dst, fs_reg *src, int sources);
-
- fs_inst(enum opcode opcode = BRW_OPCODE_NOP, const fs_reg &dst = reg_undef);
- fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0);
- fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
- const fs_reg &src1);
- fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
- const fs_reg &src1, const fs_reg &src2);
- fs_inst(enum opcode opcode, const fs_reg &dst, fs_reg src[], int sources);
+ fs_inst();
+ fs_inst(enum opcode opcode, uint8_t exec_width,
+ const fs_reg &dst = reg_undef);
+ fs_inst(enum opcode opcode, uint8_t exec_width, const fs_reg &dst,
+ const fs_reg &src0);
+ fs_inst(enum opcode opcode, uint8_t exec_width, const fs_reg &dst,
+ const fs_reg &src0, const fs_reg &src1);
+ fs_inst(enum opcode opcode, uint8_t exec_width, const fs_reg &dst,
+ const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
+ fs_inst(enum opcode opcode, uint8_t exec_width, const fs_reg &dst,
+ fs_reg src[], int sources);
fs_inst(const fs_inst &that);
void resize_sources(uint8_t num_sources);
@@ -184,6 +189,13 @@ public:
uint8_t sources; /**< Number of fs_reg sources. */
+ /**
+ * Execution width of the instruction. This is used by the generator to
+ * generate the correct binary for the given fs_inst. Current valid
+ * values are 1, 8, 16.
+ */
+ uint8_t width;
+
/* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
* mod and predication.
*/
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index a9bff65..64cb056 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -545,7 +545,7 @@ fs_visitor::emit_unspill(bblock_t *block, fs_inst *inst, fs_reg dst,
new(mem_ctx) fs_inst(gen7_read ?
SHADER_OPCODE_GEN7_SCRATCH_READ :
SHADER_OPCODE_GEN4_SCRATCH_READ,
- dst);
+ dispatch_width, dst);
unspill_inst->offset = spill_offset;
unspill_inst->ir = inst->ir;
unspill_inst->annotation = inst->annotation;
@@ -715,7 +715,7 @@ fs_visitor::spill_reg(int spill_reg)
for (int chan = 0; chan < inst->regs_written; chan++) {
fs_inst *spill_inst =
new(mem_ctx) fs_inst(SHADER_OPCODE_GEN4_SCRATCH_WRITE,
- reg_null_f, spill_src);
+ dispatch_width, reg_null_f, spill_src);
spill_src.reg_offset++;
spill_inst->offset = subset_spill_offset + chan * reg_size;
spill_inst->ir = inst->ir;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 0206fb0..a8c24e8 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -940,7 +940,7 @@ fs_visitor::visit(ir_expression *ir)
packed_consts.type = result.type;
fs_reg const_offset_reg = fs_reg(const_offset->value.u[0] & ~15);
- emit(new(mem_ctx) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
+ emit(new(mem_ctx) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD, 8,
packed_consts, surf_index, const_offset_reg));
for (int i = 0; i < ir->type->vector_elements; i++) {
--
2.1.0
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