[Mesa-dev] [PATCH 03/10] i965/fs: Properly set the instruction width for atomics and surface reads

[Jason Ekstrand]

Signed-off-by: Jason Ekstrand <jason.ekstrand at intel.com>
---
 src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 30 +++++++++++++++-------------
 1 file changed, 16 insertions(+), 14 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index a8c24e8..61b026b 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -2688,17 +2688,18 @@ fs_visitor::emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
    fs_inst *inst;
 
    /* Initialize the sample mask in the message header. */
-   emit(MOV(brw_uvec_mrf(8, mlen, 0), fs_reg(0u)))
-      ->force_writemask_all = true;
+   inst = emit(MOV(brw_uvec_mrf(8, mlen, 0), fs_reg(0u)));
+   inst->force_writemask_all = true;
+   inst->width = 8;
 
    if (fp->UsesKill) {
-      emit(MOV(brw_uvec_mrf(1, mlen, 7), brw_flag_reg(0, 1)))
-         ->force_writemask_all = true;
+      inst = emit(MOV(brw_uvec_mrf(1, mlen, 7), brw_flag_reg(0, 1)));
    } else {
-      emit(MOV(brw_uvec_mrf(1, mlen, 7),
-               retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD)))
-         ->force_writemask_all = true;
+      inst = emit(MOV(brw_uvec_mrf(1, mlen, 7),
+                      retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD)));
    }
+   inst->force_writemask_all = true;
+   inst->width = 1;
 
    mlen++;
 
@@ -2733,17 +2734,18 @@ fs_visitor::emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
    fs_inst *inst;
 
    /* Initialize the sample mask in the message header. */
-   emit(MOV(brw_uvec_mrf(8, mlen, 0), fs_reg(0u)))
-      ->force_writemask_all = true;
+   inst = emit(MOV(brw_uvec_mrf(8, mlen, 0), fs_reg(0u)));
+   inst->force_writemask_all = true;
+   inst->width = 8;
 
    if (fp->UsesKill) {
-      emit(MOV(brw_uvec_mrf(1, mlen, 7), brw_flag_reg(0, 1)))
-         ->force_writemask_all = true;
+      inst = emit(MOV(brw_uvec_mrf(1, mlen, 7), brw_flag_reg(0, 1)));
    } else {
-      emit(MOV(brw_uvec_mrf(1, mlen, 7),
-               retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD)))
-         ->force_writemask_all = true;
+      inst = emit(MOV(brw_uvec_mrf(1, mlen, 7),
+                      retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD)));
    }
+   inst->force_writemask_all = true;
+   inst->width = 1;
 
    mlen++;
 
-- 
2.1.0