[Mesa-dev] [PATCH 08/10] i965/fs: Use instruction width instead of heuristics

[Jason Ekstrand]

Signed-off-by: Jason Ekstrand <jason.ekstrand at intel.com>
---
 src/mesa/drivers/dri/i965/brw_fs.cpp               | 30 ++++++++--------------
 .../drivers/dri/i965/brw_fs_live_variables.cpp     | 10 ++++----
 .../drivers/dri/i965/brw_schedule_instructions.cpp |  4 +--
 3 files changed, 16 insertions(+), 28 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 15c68be..2d1e601 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -2185,8 +2185,7 @@ fs_visitor::compute_to_mrf()
       int mrf_high;
       if (inst->dst.reg & BRW_MRF_COMPR4) {
 	 mrf_high = mrf_low + 4;
-      } else if (dispatch_width == 16 &&
-		 (!inst->force_uncompressed && !inst->force_sechalf)) {
+      } else if (inst->width == 16) {
 	 mrf_high = mrf_low + 1;
       } else {
 	 mrf_high = mrf_low;
@@ -2279,9 +2278,7 @@ fs_visitor::compute_to_mrf()
 
 	    if (scan_inst->dst.reg & BRW_MRF_COMPR4) {
 	       scan_mrf_high = scan_mrf_low + 4;
-	    } else if (dispatch_width == 16 &&
-		       (!scan_inst->force_uncompressed &&
-			!scan_inst->force_sechalf)) {
+	    } else if (scan_inst->width == 16) {
 	       scan_mrf_high = scan_mrf_low + 1;
 	    } else {
 	       scan_mrf_high = scan_mrf_low;
@@ -2488,10 +2485,6 @@ static void
 clear_deps_for_inst_src(fs_inst *inst, int dispatch_width, bool *deps,
                         int first_grf, int grf_len)
 {
-   bool inst_simd16 = (dispatch_width > 8 &&
-                       !inst->force_uncompressed &&
-                       !inst->force_sechalf);
-
    /* Clear the flag for registers that actually got read (as expected). */
    for (int i = 0; i < inst->sources; i++) {
       int grf;
@@ -2507,7 +2500,7 @@ clear_deps_for_inst_src(fs_inst *inst, int dispatch_width, bool *deps,
       if (grf >= first_grf &&
           grf < first_grf + grf_len) {
          deps[grf - first_grf] = false;
-         if (inst_simd16)
+         if (inst->width == 16)
             deps[grf - first_grf + 1] = false;
       }
    }
@@ -2565,10 +2558,6 @@ fs_visitor::insert_gen4_pre_send_dependency_workarounds(fs_inst *inst)
          return;
       }
 
-      bool scan_inst_simd16 = (dispatch_width > 8 &&
-                               !scan_inst->force_uncompressed &&
-                               !scan_inst->force_sechalf);
-
       /* We insert our reads as late as possible on the assumption that any
        * instruction but a MOV that might have left us an outstanding
        * dependency has more latency than a MOV.
@@ -2582,7 +2571,7 @@ fs_visitor::insert_gen4_pre_send_dependency_workarounds(fs_inst *inst)
                 needs_dep[reg - first_write_grf]) {
                inst->insert_before(DEP_RESOLVE_MOV(reg));
                needs_dep[reg - first_write_grf] = false;
-               if (scan_inst_simd16)
+               if (scan_inst->width == 16)
                   needs_dep[reg - first_write_grf + 1] = false;
             }
          }
@@ -3004,11 +2993,12 @@ fs_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
 
    fprintf(file, " ");
 
-   if (inst->force_uncompressed)
-      fprintf(file, "1sthalf ");
-
-   if (inst->force_sechalf)
-      fprintf(file, "2ndhalf ");
+   if (inst->width == 16) {
+      if (inst->force_sechalf)
+         fprintf(file, "2ndhalf ");
+      else
+         fprintf(file, "1sthalf ");
+   }
 
    fprintf(file, "\n");
 }
diff --git a/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp b/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp
index e7ecb0f..160bf71 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp
@@ -85,11 +85,11 @@ fs_live_variables::setup_one_read(bblock_t *block, fs_inst *inst,
     * would get stomped by the first decode as well.
     */
    int end_ip = ip;
-   if (v->dispatch_width == 16 && (reg.stride == 0 ||
-                                   reg.type == BRW_REGISTER_TYPE_UW ||
-                                   reg.type == BRW_REGISTER_TYPE_W ||
-                                   reg.type == BRW_REGISTER_TYPE_UB ||
-                                   reg.type == BRW_REGISTER_TYPE_B)) {
+   if (inst->width == 16 && (reg.stride == 0 ||
+                             reg.type == BRW_REGISTER_TYPE_UW ||
+                             reg.type == BRW_REGISTER_TYPE_W ||
+                             reg.type == BRW_REGISTER_TYPE_UB ||
+                             reg.type == BRW_REGISTER_TYPE_B)) {
       end_ip++;
    }
 
diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
index 04ac242..1b6020c 100644
--- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
@@ -734,9 +734,7 @@ instruction_scheduler::add_barrier_deps(schedule_node *n)
 bool
 fs_instruction_scheduler::is_compressed(fs_inst *inst)
 {
-   return (v->dispatch_width == 16 &&
-	   !inst->force_uncompressed &&
-	   !inst->force_sechalf);
+   return inst->width == 16;
 }
 
 void
-- 
2.1.0