[Mesa-dev] [PATCH 01/37] i965/gs: Use single dispatch mode as fallback to dual object mode when possible.

[Iago Toral Quiroga]

On mar, 2014-09-16 at 01:10 -0700, Kenneth Graunke wrote:
> On Thursday, September 04, 2014 09:36:34 AM Iago Toral Quiroga wrote:
> > On jue, 2014-09-04 at 00:07 -0700, Jordan Justen wrote:
> > > On Wed, Sep 3, 2014 at 11:28 PM, Iago Toral Quiroga <itoral at igalia.com> wrote:
> > > > On mié, 2014-09-03 at 17:49 -0700, Jordan Justen wrote:
> > > >> On Thu, Aug 14, 2014 at 4:11 AM, Iago Toral Quiroga <itoral at igalia.com> wrote:
> > > >> > Currently, when a geometry shader can't use dual object mode we fall back to
> > > >> > dual instance mode, however, when invocations == 1, single dispatch mode is
> > > >> > more performant and equally efficient in terms of register pressure.
> > > >> >
> > > >> > Single dispatch mode requires that the driver can handle interleaving of
> > > >> > registers, but this is already supported (dual instance mode has the same
> > > >> > requirement).
> > > 
> > > Maybe this paragraph could use a minor clarification too? (Of what is
> > > required vs. optional. And the fact that we're not doing the optional
> > > one.)
> > 
> > Sure. How about this?:
> > 
> > Single dispatch mode requires that the driver can handle interleaving of
> > input registers, but this is already supported (dual instance mode has
> > the same requirement). However, to take full advantage of single
> > dispatch mode to reduce register pressure we would also need to do
> > interleaved outputs, but currently, the vec4 visitor and generator
> > classes do not support this, so at the moment register pressure in
> > single and dual instance modes is the same.
> 
> I'm not sure about "interleaved outputs".  Really, the idea is that we want to be able to store two separate vec4 values in a single vec8 register, i.e. register allocating to both r3.0 and r3.4.  Which would provide approximately double the register space for ordinary temporary values.
> 
> Just a thought.  I'm sure whatever you write in the comments will be fine.

Right, this is more general than simply interleaving the outputs. I
think I will just use the explanation you wrote directly:

(...) However, to take full advantage of single dispatch mode to reduce
register pressure we would also need to ability to store two separate
vec4 output values into vec8 registers, which would approximately double
our capacity to store temporary values, but currently the vec4 visitor
and generator classes do not support this, (...)

Iago