[Mesa-dev] [PATCH 14/20] i965/vec4: Don't iterate between blocks with inst->next/prev.

Matt Turner mattst88 at gmail.com
Fri Sep 19 19:27:55 PDT 2014


On Wed, Sep 17, 2014 at 5:51 AM, Pohjolainen, Topi
<topi.pohjolainen at intel.com> wrote:
> On Tue, Sep 02, 2014 at 09:34:25PM -0700, Matt Turner wrote:
>> The register coalescing portion of this patch hurts three shaders in
>> Guacamelee by one instruction each, but examining the diff makes me
>> believe that what we were generating was (perhaps harmlessly) incorrect.
>> ---
>>  src/mesa/drivers/dri/i965/brw_vec4.cpp | 30 +++++++++---------------------
>>  1 file changed, 9 insertions(+), 21 deletions(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
>> index 6669281..e3869d6 100644
>> --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
>> @@ -513,12 +513,9 @@ vec4_visitor::dead_code_eliminate()
>>           }
>>        }
>>
>> -      for (exec_node *node = inst->prev, *prev = node->prev;
>> -           prev != NULL && dead_channels != 0;
>> -           node = prev, prev = prev->prev) {
>> -         vec4_instruction *scan_inst = (vec4_instruction  *)node;
>> -
>> -         if (scan_inst->is_control_flow())
>
> Last instruction of the block is not considered in the iteration, but first
> instruction is. Hence if I'm reading this right, before DO and ENDIF weren't
> considered but now they are.

That's true, but it doesn't have any effect, since neither do nor
endif take arguments.


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