[Mesa-dev] [PATCH 4/4] radeonsi: remove old cache flushing code

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/drivers/radeonsi/si_commands.c | 21 -----------------
 src/gallium/drivers/radeonsi/si_pm4.c      | 36 +-----------------------------
 src/gallium/drivers/radeonsi/si_pm4.h      |  9 --------
 src/gallium/drivers/radeonsi/si_state.h    |  1 -
 4 files changed, 1 insertion(+), 66 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_commands.c b/src/gallium/drivers/radeonsi/si_commands.c
index 2efdeda..bf1cb30 100644
--- a/src/gallium/drivers/radeonsi/si_commands.c
+++ b/src/gallium/drivers/radeonsi/si_commands.c
@@ -109,24 +109,3 @@ void si_cmd_draw_index_indirect(struct si_pm4_state *pm4, uint64_t indirect_va,
 	si_pm4_cmd_add(pm4, V_0287F0_DI_SRC_SEL_DMA);
 	si_pm4_cmd_end(pm4, predicate);
 }
-
-void si_cmd_surface_sync(struct si_pm4_state *pm4, uint32_t cp_coher_cntl)
-{
-	if (pm4->chip_class >= CIK) {
-		si_pm4_cmd_begin(pm4, PKT3_ACQUIRE_MEM);
-		si_pm4_cmd_add(pm4, cp_coher_cntl);	/* CP_COHER_CNTL */
-		si_pm4_cmd_add(pm4, 0xffffffff);	/* CP_COHER_SIZE */
-		si_pm4_cmd_add(pm4, 0xff);		/* CP_COHER_SIZE_HI */
-		si_pm4_cmd_add(pm4, 0);			/* CP_COHER_BASE */
-		si_pm4_cmd_add(pm4, 0);			/* CP_COHER_BASE_HI */
-		si_pm4_cmd_add(pm4, 0x0000000A);	/* POLL_INTERVAL */
-		si_pm4_cmd_end(pm4, false);
-	} else {
-		si_pm4_cmd_begin(pm4, PKT3_SURFACE_SYNC);
-		si_pm4_cmd_add(pm4, cp_coher_cntl);	/* CP_COHER_CNTL */
-		si_pm4_cmd_add(pm4, 0xffffffff);	/* CP_COHER_SIZE */
-		si_pm4_cmd_add(pm4, 0);			/* CP_COHER_BASE */
-		si_pm4_cmd_add(pm4, 0x0000000A);	/* POLL_INTERVAL */
-		si_pm4_cmd_end(pm4, false);
-	}
-}
diff --git a/src/gallium/drivers/radeonsi/si_pm4.c b/src/gallium/drivers/radeonsi/si_pm4.c
index 61ebad5..0b872b8 100644
--- a/src/gallium/drivers/radeonsi/si_pm4.c
+++ b/src/gallium/drivers/radeonsi/si_pm4.c
@@ -103,18 +103,6 @@ void si_pm4_add_bo(struct si_pm4_state *state,
 	state->bo_priority[idx] = priority;
 }
 
-void si_pm4_inval_shader_cache(struct si_pm4_state *state)
-{
-	state->cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
-	state->cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
-}
-
-void si_pm4_inval_texture_cache(struct si_pm4_state *state)
-{
-	state->cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1);
-	state->cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1);
-}
-
 void si_pm4_free_state(struct si_context *sctx,
 		       struct si_pm4_state *state,
 		       unsigned idx)
@@ -134,29 +122,7 @@ void si_pm4_free_state(struct si_context *sctx,
 
 struct si_pm4_state * si_pm4_alloc_state(struct si_context *sctx)
 {
-	struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
-
-        if (pm4 == NULL)
-                return NULL;
-
-	pm4->chip_class = sctx->b.chip_class;
-
-	return pm4;
-}
-
-uint32_t si_pm4_sync_flags(struct si_context *sctx)
-{
-	uint32_t cp_coher_cntl = 0;
-
-	for (int i = 0; i < NUMBER_OF_STATES; ++i) {
-		struct si_pm4_state *state = sctx->queued.array[i];
-
-		if (!state || sctx->emitted.array[i] == state)
-			continue;
-
-		cp_coher_cntl |= state->cp_coher_cntl;
-	}
-	return cp_coher_cntl;
+	return CALLOC_STRUCT(si_pm4_state);
 }
 
 unsigned si_pm4_dirty_dw(struct si_context *sctx)
diff --git a/src/gallium/drivers/radeonsi/si_pm4.h b/src/gallium/drivers/radeonsi/si_pm4.h
index c7e032a..f234286 100644
--- a/src/gallium/drivers/radeonsi/si_pm4.h
+++ b/src/gallium/drivers/radeonsi/si_pm4.h
@@ -39,16 +39,11 @@ enum chip_class;
 
 struct si_pm4_state
 {
-	/* family specific handling */
-	enum chip_class chip_class;
 	/* PKT3_SET_*_REG handling */
 	unsigned	last_opcode;
 	unsigned	last_reg;
 	unsigned	last_pm4;
 
-	/* flush flags for SURFACE_SYNC */
-	uint32_t	cp_coher_cntl;
-
 	/* commands for the DE */
 	unsigned	ndw;
 	uint32_t	pm4[SI_PM4_MAX_DW];
@@ -76,15 +71,11 @@ void si_pm4_add_bo(struct si_pm4_state *state,
 		   enum radeon_bo_usage usage,
 		   enum radeon_bo_priority priority);
 
-void si_pm4_inval_shader_cache(struct si_pm4_state *state);
-void si_pm4_inval_texture_cache(struct si_pm4_state *state);
-
 void si_pm4_free_state(struct si_context *sctx,
 		       struct si_pm4_state *state,
 		       unsigned idx);
 struct si_pm4_state * si_pm4_alloc_state(struct si_context *sctx);
 
-uint32_t si_pm4_sync_flags(struct si_context *sctx);
 unsigned si_pm4_dirty_dw(struct si_context *sctx);
 void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state);
 void si_pm4_emit_dirty(struct si_context *sctx);
diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index d3a745a..7b6de6b 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -286,6 +286,5 @@ void si_cmd_draw_index_indirect(struct si_pm4_state *pm4, uint64_t indirect_va,
 				uint64_t index_va, uint32_t index_max_size,
 				uint32_t indirect_offset, uint32_t base_vtx_loc,
 				uint32_t start_inst_loc, bool predicate);
-void si_cmd_surface_sync(struct si_pm4_state *pm4, uint32_t cp_coher_cntl);
 
 #endif
-- 
1.9.1