[Mesa-dev] [PATCH 32/41] i965/fs: Use instruction execution sizes instead of heuristics
Jason Ekstrand
jason at jlekstrand.net
Sat Sep 20 10:23:21 PDT 2014
Signed-off-by: Jason Ekstrand <jason.ekstrand at intel.com>
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 19 ++++---------------
src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp | 10 +++++-----
.../drivers/dri/i965/brw_schedule_instructions.cpp | 4 +---
3 files changed, 10 insertions(+), 23 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 41ce22f..e06e083 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -2415,8 +2415,7 @@ fs_visitor::compute_to_mrf()
int mrf_high;
if (inst->dst.reg & BRW_MRF_COMPR4) {
mrf_high = mrf_low + 4;
- } else if (dispatch_width == 16 &&
- (!inst->force_uncompressed && !inst->force_sechalf)) {
+ } else if (inst->exec_size == 16) {
mrf_high = mrf_low + 1;
} else {
mrf_high = mrf_low;
@@ -2509,9 +2508,7 @@ fs_visitor::compute_to_mrf()
if (scan_inst->dst.reg & BRW_MRF_COMPR4) {
scan_mrf_high = scan_mrf_low + 4;
- } else if (dispatch_width == 16 &&
- (!scan_inst->force_uncompressed &&
- !scan_inst->force_sechalf)) {
+ } else if (scan_inst->exec_size == 16) {
scan_mrf_high = scan_mrf_low + 1;
} else {
scan_mrf_high = scan_mrf_low;
@@ -2666,10 +2663,6 @@ static void
clear_deps_for_inst_src(fs_inst *inst, int dispatch_width, bool *deps,
int first_grf, int grf_len)
{
- bool inst_simd16 = (dispatch_width > 8 &&
- !inst->force_uncompressed &&
- !inst->force_sechalf);
-
/* Clear the flag for registers that actually got read (as expected). */
for (int i = 0; i < inst->sources; i++) {
int grf;
@@ -2685,7 +2678,7 @@ clear_deps_for_inst_src(fs_inst *inst, int dispatch_width, bool *deps,
if (grf >= first_grf &&
grf < first_grf + grf_len) {
deps[grf - first_grf] = false;
- if (inst_simd16)
+ if (inst->exec_size == 16)
deps[grf - first_grf + 1] = false;
}
}
@@ -2742,10 +2735,6 @@ fs_visitor::insert_gen4_pre_send_dependency_workarounds(fs_inst *inst)
return;
}
- bool scan_inst_simd16 = (dispatch_width > 8 &&
- !scan_inst->force_uncompressed &&
- !scan_inst->force_sechalf);
-
/* We insert our reads as late as possible on the assumption that any
* instruction but a MOV that might have left us an outstanding
* dependency has more latency than a MOV.
@@ -2759,7 +2748,7 @@ fs_visitor::insert_gen4_pre_send_dependency_workarounds(fs_inst *inst)
needs_dep[reg - first_write_grf]) {
inst->insert_before(DEP_RESOLVE_MOV(reg));
needs_dep[reg - first_write_grf] = false;
- if (scan_inst_simd16)
+ if (scan_inst->exec_size == 16)
needs_dep[reg - first_write_grf + 1] = false;
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp b/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp
index 39fc61a..779645a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp
@@ -85,11 +85,11 @@ fs_live_variables::setup_one_read(bblock_t *block, fs_inst *inst,
* would get stomped by the first decode as well.
*/
int end_ip = ip;
- if (v->dispatch_width == 16 && (reg.stride == 0 ||
- reg.type == BRW_REGISTER_TYPE_UW ||
- reg.type == BRW_REGISTER_TYPE_W ||
- reg.type == BRW_REGISTER_TYPE_UB ||
- reg.type == BRW_REGISTER_TYPE_B)) {
+ if (inst->exec_size == 16 && (reg.stride == 0 ||
+ reg.type == BRW_REGISTER_TYPE_UW ||
+ reg.type == BRW_REGISTER_TYPE_W ||
+ reg.type == BRW_REGISTER_TYPE_UB ||
+ reg.type == BRW_REGISTER_TYPE_B)) {
end_ip++;
}
diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
index a9fa6eb..2a768dd 100644
--- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
@@ -734,9 +734,7 @@ instruction_scheduler::add_barrier_deps(schedule_node *n)
bool
fs_instruction_scheduler::is_compressed(fs_inst *inst)
{
- return (v->dispatch_width == 16 &&
- !inst->force_uncompressed &&
- !inst->force_sechalf);
+ return inst->exec_size == 16;
}
void
--
2.1.0
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