[Mesa-dev] [PATCH 05/16] i965/skl: Update stencil reference handling for Skylake.
Kristian Høgsberg
krh at bitplanet.net
Wed Sep 24 12:28:10 PDT 2014
From: Kenneth Graunke <kenneth at whitecape.org>
Skylake uploads the stencil reference values in DW3 of the
3DSTATE_WM_DEPTH_STENCIL packet, rather than in COLOR_CALC_STATE.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
---
src/mesa/drivers/dri/i965/brw_defines.h | 5 +++++
src/mesa/drivers/dri/i965/gen6_cc.c | 9 ++++++---
src/mesa/drivers/dri/i965/gen8_wm_depth_stencil.c | 20 +++++++++++++++++---
3 files changed, 28 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index aca78af..3953924 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -2033,6 +2033,11 @@ enum brw_message_target {
# define GEN8_WM_DS_BF_STENCIL_TEST_MASK_SHIFT 8
# define GEN8_WM_DS_BF_STENCIL_WRITE_MASK_MASK INTEL_MASK(7, 0)
# define GEN8_WM_DS_BF_STENCIL_WRITE_MASK_SHIFT 0
+/* DW3 */
+# define GEN9_WM_DS_STENCIL_REF_MASK INTEL_MASK(15, 8)
+# define GEN9_WM_DS_STENCIL_REF_SHIFT 8
+# define GEN9_WM_DS_BF_STENCIL_REF_MASK INTEL_MASK(7, 0)
+# define GEN9_WM_DS_BF_STENCIL_REF_SHIFT 0
#define _3DSTATE_PS_EXTRA 0x784F /* GEN8+ */
/* DW1 */
diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c b/src/mesa/drivers/dri/i965/gen6_cc.c
index 45c926c..4770063 100644
--- a/src/mesa/drivers/dri/i965/gen6_cc.c
+++ b/src/mesa/drivers/dri/i965/gen6_cc.c
@@ -264,9 +264,12 @@ gen6_upload_color_calc_state(struct brw_context *brw)
cc->cc0.alpha_test_format = BRW_ALPHATEST_FORMAT_UNORM8;
UNCLAMPED_FLOAT_TO_UBYTE(cc->cc1.alpha_ref_fi.ui, ctx->Color.AlphaRef);
- /* _NEW_STENCIL */
- cc->cc0.stencil_ref = _mesa_get_stencil_ref(ctx, 0);
- cc->cc0.bf_stencil_ref = _mesa_get_stencil_ref(ctx, ctx->Stencil._BackFace);
+ if (brw->gen < 9) {
+ /* _NEW_STENCIL */
+ cc->cc0.stencil_ref = _mesa_get_stencil_ref(ctx, 0);
+ cc->cc0.bf_stencil_ref =
+ _mesa_get_stencil_ref(ctx, ctx->Stencil._BackFace);
+ }
/* _NEW_COLOR */
cc->constant_r = ctx->Color.BlendColorUnclamped[0];
diff --git a/src/mesa/drivers/dri/i965/gen8_wm_depth_stencil.c b/src/mesa/drivers/dri/i965/gen8_wm_depth_stencil.c
index 8f5728f..38212cd 100644
--- a/src/mesa/drivers/dri/i965/gen8_wm_depth_stencil.c
+++ b/src/mesa/drivers/dri/i965/gen8_wm_depth_stencil.c
@@ -26,12 +26,13 @@
#include "brw_context.h"
#include "brw_defines.h"
#include "brw_state.h"
+#include "main/stencil.h"
static void
gen8_upload_wm_depth_stencil(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
- uint32_t dw1 = 0, dw2 = 0;
+ uint32_t dw1 = 0, dw2 = 0, dw3 = 0;
/* _NEW_BUFFERS */
struct intel_renderbuffer *depth_irb =
@@ -73,6 +74,14 @@ gen8_upload_wm_depth_stencil(struct brw_context *brw)
SET_FIELD(stencil->ValueMask[b] & 0xff,
GEN8_WM_DS_BF_STENCIL_TEST_MASK);
}
+
+ if (brw->gen >= 9) {
+ int stencil_ref = _mesa_get_stencil_ref(ctx, 0);
+ int backface_ref = _mesa_get_stencil_ref(ctx, ctx->Stencil._BackFace);
+
+ dw3 = SET_FIELD(stencil_ref, GEN9_WM_DS_STENCIL_REF) |
+ SET_FIELD(backface_ref, GEN9_WM_DS_BF_STENCIL_REF);
+ }
}
/* _NEW_DEPTH */
@@ -85,10 +94,15 @@ gen8_upload_wm_depth_stencil(struct brw_context *brw)
dw1 |= GEN8_WM_DS_DEPTH_BUFFER_WRITE_ENABLE;
}
- BEGIN_BATCH(3);
- OUT_BATCH(_3DSTATE_WM_DEPTH_STENCIL << 16 | (3 - 2));
+ int pkt_len = brw->gen >= 9 ? 4 : 3;
+
+ BEGIN_BATCH(pkt_len);
+ OUT_BATCH(_3DSTATE_WM_DEPTH_STENCIL << 16 | (pkt_len - 2));
OUT_BATCH(dw1);
OUT_BATCH(dw2);
+ if (pkt_len > 3) {
+ OUT_BATCH(dw3);
+ }
ADVANCE_BATCH();
}
--
2.1.0
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