[Mesa-dev] [PATCH 08/16] i965/skl: Allocate 16 DWords for SURFACE_STATE on Skylake.

[Kenneth Graunke]

On Wednesday, September 24, 2014 12:28:13 PM Kristian Høgsberg wrote:
> From: Kenneth Graunke <kenneth at whitecape.org>
> 
> Otherwise they overlap and horrible things happen.  All the new DWords
> are for fast color clear values, which we don't do yet.

This is no longer true.  I see nothing prohibiting fast color clears from happening on Skylake, but with this patch alone, we don't set up the fast color clear values properly.  So, it will almost certainly break (or at least always clear to black).

I would probably recommend disabling fast color clears at this point, and then send a later patch that fills in the proper info and turns them on.  But it's your call.
 
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
> ---
>  src/mesa/drivers/dri/i965/gen8_surface_state.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
> index f399029..1742012 100644
> --- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
> @@ -84,7 +84,7 @@ horizontal_alignment(struct intel_mipmap_tree *mt)
>  static uint32_t *
>  allocate_surface_state(const struct brw_context *brw, uint32_t *out_offset)
>  {
> -   int dwords = 13;
> +   int dwords = brw->gen >= 9 ? 16 : 13;
>     uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
>                                      dwords * 4, 64, out_offset);
>     memset(surf, 0, dwords * 4);
> 
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