[Mesa-dev] [PATCH 2/2] i965: Use BDW_MOCS_PTE for renderbuffers.

[Daniel Vetter]

On Tue, Sep 30, 2014 at 01:15:56AM -0700, Kenneth Graunke wrote:
> Write-back caching cannot be used for buffers being scanned out by the
> display engine; surfaces used for scan-out must be write-through or
> uncached.  I originally chose WT for render targets because it works in
> all cases.  However, we really want to use write-back caching where
> possible, as it is more efficient.
> 
> Most renderbuffers are not used for scanout - off-screen FBOs certainly
> are fine, and non-pageflipped backbuffers should be fine as well.  So
> in most cases WB will work.  However, we don't know what will be used
> for scan-out, so we instead simply use the PTE value specified by the
> kernel, as it knows these things.
> 
> This matches our MOCS choice on Haswell.
> 
> Fixes performance regressions since commit ee4484be3dc827cf15bcf109f5
> in a microbenchmark (spotted by Eero Tamminen).  Improves performance
> in GLBenchmark 2.7/EgyptHD by 7.44362% +/- 0.496939% (n=55) on a
> Broadwell GT2.
> 
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> Reported-by: Eero Tamminen <eero.t.tamminen at intel.com>
> Cc: mesa-stable at lists.freedesktop.org
> ---
>  src/mesa/drivers/dri/i965/gen8_surface_state.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> Cc'd to stable because it's a pretty trivial change and provides a sizable
> boost to performance on new hardware.

Both patches are Reviewed-by: Daniel Vetter <daniel.vetter at ffwll.ch>

Aside: Not using WT on display can lead to corruption (apparently bdw is
fairly aggressive with writeback so hard to spot in reality), so imo
definitely stable material.

With the hw display crc stuff we now support in the kernel/igt we could
even write an automated testcase for these corruptions, but probably not
worth the hassle.
-Daniel

> 
> diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
> index 40eb2ea..6dd343f 100644
> --- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
> @@ -377,7 +377,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
>               horizontal_alignment(mt) |
>               surface_tiling_mode(tiling);
>  
> -   surf[1] = SET_FIELD(BDW_MOCS_WT, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
> +   surf[1] = SET_FIELD(BDW_MOCS_PTE, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
>  
>     surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
>               SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
> -- 
> 2.1.1
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch