[Mesa-dev] [PATCH v3 0/4] Improvements to the vec4 spilling code

[Iago Toral Quiroga]

Link to v1:
http://lists.freedesktop.org/archives/mesa-dev/2015-July/089766.html

Link to v2:
http://lists.freedesktop.org/archives/mesa-dev/2015-July/089958.html

Changes in v3 (Curro):
  - Move the caching logic to a separate helper function and reuse it in both
    spill_reg and evaluate_spill_cost
  - Make unspills in spill_reg always load a full vec4 so we can benefit
    the optimization

Iago Toral Quiroga (4):
  i965: Add a debug option for spilling everything in vec4 code
  i965/vec4: do not predicate scratch writes for BRW_OPCODE_SEL
    instructions
  i965/vec4: Fix indentation in vec4_visitor::evaluate_spill_costs
  i965/vec4: Don't unspill the same register in consecutive instructions

 src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp  |   2 +-
 src/mesa/drivers/dri/i965/brw_vec4.cpp             |   2 +-
 .../drivers/dri/i965/brw_vec4_reg_allocate.cpp     | 151 ++++++++++++++++++---
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp     |   3 +-
 src/mesa/drivers/dri/i965/intel_debug.c            |   3 +-
 src/mesa/drivers/dri/i965/intel_debug.h            |   5 +-
 6 files changed, 141 insertions(+), 25 deletions(-)

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1.9.1