[Mesa-dev] [PATCH 1/5] i965: Define virtual instruction to calculate the high 32 bits of a multiply.

[Ilia Mirkin]

On Wed, Aug 5, 2015 at 2:03 PM, Ilia Mirkin <imirkin at alum.mit.edu> wrote:
> On Wed, Aug 5, 2015 at 1:52 PM, Francisco Jerez <currojerez at riseup.net> wrote:
>> This instruction will translate to the MUL/MACH sequence that computes
>> the high 32-bits of the result of a 64-bit multiply.  Before Gen8
>
> Unlike with 32x32 -> low 32, you need to specify if it's a signed or
> unsigned multiply. s32 x s32 -> high 32 takes a bunch of extra effort
> if you're splitting the multiply up into 32-bit chunks.

Oh I see (from later patches) that you actually have type information
on the sources, so nevermind!

>
> By the way, ARB_gpu_shader5 introduced umulExtended and imulExtended
> which produce the full 64-bit result for both variants... I would have
> assumed this would already be somehow handled in i965.
>
>> integer operations that used the accumulator were limited to 8-wide,
>> but the SIMD lowering pass can easily be hooked up to sidestep this
>> limitation, we just need a virtual opcode to represent the MUL/MACH
>> sequence in the IR.
>> ---
>>  src/mesa/drivers/dri/i965/brw_defines.h                 | 5 +++++
>>  src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp   | 1 +
>>  src/mesa/drivers/dri/i965/brw_fs_cse.cpp                | 1 +
>>  src/mesa/drivers/dri/i965/brw_shader.cpp                | 4 ++++
>>  src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp | 1 +
>>  src/mesa/drivers/dri/i965/brw_vec4_cse.cpp              | 1 +
>>  6 files changed, 13 insertions(+)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
>> index f595366..9c232c4 100644
>> --- a/src/mesa/drivers/dri/i965/brw_defines.h
>> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
>> @@ -1214,6 +1214,11 @@ enum opcode {
>>      * GLSL barrier()
>>      */
>>     SHADER_OPCODE_BARRIER,
>> +
>> +   /**
>> +    * Calculate the high 32-bits of a 32x32 multiply.
>> +    */
>> +   SHADER_OPCODE_MULH,
>>  };
>>
>>  enum brw_urb_write_flags {
>> diff --git a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
>> index 3940158..a4fb21d 100644
>> --- a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
>> @@ -534,6 +534,7 @@ fs_visitor::try_constant_propagate(fs_inst *inst, acp_entry *entry)
>>
>>        case BRW_OPCODE_MACH:
>>        case BRW_OPCODE_MUL:
>> +      case SHADER_OPCODE_MULH:
>>        case BRW_OPCODE_ADD:
>>        case BRW_OPCODE_OR:
>>        case BRW_OPCODE_AND:
>> diff --git a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
>> index a123ff2..c7628dc 100644
>> --- a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
>> @@ -61,6 +61,7 @@ is_expression(const fs_visitor *v, const fs_inst *const inst)
>>     case BRW_OPCODE_CMPN:
>>     case BRW_OPCODE_ADD:
>>     case BRW_OPCODE_MUL:
>> +   case SHADER_OPCODE_MULH:
>>     case BRW_OPCODE_FRC:
>>     case BRW_OPCODE_RNDU:
>>     case BRW_OPCODE_RNDD:
>> diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
>> index 819e4f2..bccf8d6 100644
>> --- a/src/mesa/drivers/dri/i965/brw_shader.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
>> @@ -778,6 +778,8 @@ brw_instruction_name(enum opcode op)
>>        return "cs_terminate";
>>     case SHADER_OPCODE_BARRIER:
>>        return "barrier";
>> +   case SHADER_OPCODE_MULH:
>> +      return "mulh";
>>     }
>>
>>     unreachable("not reached");
>> @@ -996,6 +998,7 @@ backend_instruction::is_commutative() const
>>     case BRW_OPCODE_XOR:
>>     case BRW_OPCODE_ADD:
>>     case BRW_OPCODE_MUL:
>> +   case SHADER_OPCODE_MULH:
>>        return true;
>>     case BRW_OPCODE_SEL:
>>        /* MIN and MAX are commutative. */
>> @@ -1103,6 +1106,7 @@ backend_instruction::can_do_saturate() const
>>     case BRW_OPCODE_MATH:
>>     case BRW_OPCODE_MOV:
>>     case BRW_OPCODE_MUL:
>> +   case SHADER_OPCODE_MULH:
>>     case BRW_OPCODE_PLN:
>>     case BRW_OPCODE_RNDD:
>>     case BRW_OPCODE_RNDE:
>> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
>> index 2d9afa8..5a15eb8 100644
>> --- a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
>> @@ -179,6 +179,7 @@ try_constant_propagate(const struct brw_device_info *devinfo,
>>
>>     case BRW_OPCODE_MACH:
>>     case BRW_OPCODE_MUL:
>> +   case SHADER_OPCODE_MULH:
>>     case BRW_OPCODE_ADD:
>>     case BRW_OPCODE_OR:
>>     case BRW_OPCODE_AND:
>> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp b/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
>> index c9fe0ce..5a277f7 100644
>> --- a/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
>> @@ -62,6 +62,7 @@ is_expression(const vec4_instruction *const inst)
>>     case BRW_OPCODE_CMPN:
>>     case BRW_OPCODE_ADD:
>>     case BRW_OPCODE_MUL:
>> +   case SHADER_OPCODE_MULH:
>>     case BRW_OPCODE_FRC:
>>     case BRW_OPCODE_RNDU:
>>     case BRW_OPCODE_RNDD:
>> --
>> 2.4.6
>>
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