[Mesa-dev] [PATCH] gallium/radeon: add a debug flag not to use write combining (v2)

[Michel Dänzer]

On 07.08.2015 00:11, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
> 
> v2: just clear the flag before the allocation
> ---
>  src/gallium/drivers/radeon/r600_buffer_common.c | 3 +++
>  src/gallium/drivers/radeon/r600_pipe_common.c   | 1 +
>  src/gallium/drivers/radeon/r600_pipe_common.h   | 1 +
>  3 files changed, 5 insertions(+)
> 
> diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c
> index fc5f6c2..f0b31f9 100644
> --- a/src/gallium/drivers/radeon/r600_buffer_common.c
> +++ b/src/gallium/drivers/radeon/r600_buffer_common.c
> @@ -161,6 +161,9 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
>  		flags |= RADEON_FLAG_NO_CPU_ACCESS;
>  	}
>  
> +	if (rscreen->debug_flags & DBG_NO_WC)
> +		flags &= ~RADEON_FLAG_GTT_WC;
> +
>  	/* Allocate a new resource. */
>  	new_buf = rscreen->ws->buffer_create(rscreen->ws, size, alignment,
>  					     use_reusable_pool,
> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c
> index 79b4b54..b12992d 100644
> --- a/src/gallium/drivers/radeon/r600_pipe_common.c
> +++ b/src/gallium/drivers/radeon/r600_pipe_common.c
> @@ -351,6 +351,7 @@ static const struct debug_named_value common_debug_options[] = {
>  	{ "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
>  	{ "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
>  	{ "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
> +	{ "nowc", DBG_NO_WC, "Disable GTT write combining" },
>  
>  	DEBUG_NAMED_VALUE_END /* must be last */
>  };
> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
> index fbd2a21..01c4bd3 100644
> --- a/src/gallium/drivers/radeon/r600_pipe_common.h
> +++ b/src/gallium/drivers/radeon/r600_pipe_common.h
> @@ -95,6 +95,7 @@
>  #define DBG_FORCE_DMA		(1llu << 38)
>  #define DBG_PRECOMPILE		(1llu << 39)
>  #define DBG_INFO		(1llu << 40)
> +#define DBG_NO_WC		(1llu << 41)
>  
>  #define R600_MAP_BUFFER_ALIGNMENT 64
>  
> 

Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>


-- 
Earthling Michel Dänzer               |               http://www.amd.com
Libre software enthusiast             |             Mesa and X developer