[Mesa-dev] [PATCH 06/70] i965: Move the OACONTROL pipelined access check from context to screen

Chris Wilson chris at chris-wilson.co.uk
Fri Aug 7 13:13:10 PDT 2015


Similarly to the pipelined SO_OFFSET check, this moves the global HW
compatability check to the screen next to the other global checks.

Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
 src/mesa/drivers/dri/i965/intel_extensions.c | 68 +---------------------------
 src/mesa/drivers/dri/i965/intel_screen.c     | 17 +++++++
 src/mesa/drivers/dri/i965/intel_screen.h     |  3 +-
 3 files changed, 21 insertions(+), 67 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c
index 6346fbc..e7828c7 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -32,71 +32,6 @@
 #include "intel_reg.h"
 #include "utils.h"
 
-static bool
-can_write_oacontrol(struct brw_context *brw)
-{
-   if (brw->gen < 6 || brw->gen >= 8)
-      return false;
-
-   static int result = -1;
-   if (result != -1)
-      return result;
-
-   /* Set "Select Context ID" to a particular address (which is likely not a
-    * context), but leave all counting disabled.  This should be harmless.
-    */
-   const int expected_value = 0x31337000;
-   const int offset = 110;
-
-   uint32_t *data;
-   /* Set a value in a BO to a known quantity.  The workaround BO already
-    * exists and doesn't contain anything important, so we may as well use it.
-    */
-   drm_intel_bo_map(brw->workaround_bo, true);
-   data = brw->workaround_bo->virtual;
-   data[offset] = 0xffffffff;
-   drm_intel_bo_unmap(brw->workaround_bo);
-
-   /* Write OACONTROL. */
-   BEGIN_BATCH(3);
-   OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
-   OUT_BATCH(OACONTROL);
-   OUT_BATCH(expected_value);
-   ADVANCE_BATCH();
-
-   brw_emit_mi_flush(brw);
-
-   /* Save the register's value back to the buffer. */
-   BEGIN_BATCH(3);
-   OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
-   OUT_BATCH(OACONTROL);
-   OUT_RELOC(brw->workaround_bo,
-             I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
-             offset * sizeof(uint32_t));
-   ADVANCE_BATCH();
-
-   brw_emit_mi_flush(brw);
-
-   /* Set OACONTROL back to zero (everything off). */
-   BEGIN_BATCH(3);
-   OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
-   OUT_BATCH(OACONTROL);
-   OUT_BATCH(0);
-   ADVANCE_BATCH();
-
-   intel_batchbuffer_flush(brw);
-
-   /* Check whether the value got written. */
-   drm_intel_bo_map(brw->workaround_bo, false);
-   data = brw->workaround_bo->virtual;
-   bool success = data[offset] == expected_value;
-   drm_intel_bo_unmap(brw->workaround_bo);
-
-   result = success;
-
-   return success;
-}
-
 /**
  * Initializes potential list of extensions if ctx == NULL, or actually enables
  * extensions for a context.
@@ -207,7 +142,8 @@ intelInitExtensions(struct gl_context *ctx)
       ctx->Extensions.EXT_shader_integer_mix = ctx->Const.GLSLVersion >= 130;
       ctx->Extensions.EXT_timer_query = true;
 
-      if (brw->gen == 5 || can_write_oacontrol(brw)) {
+      if (brw->gen == 5 ||
+          brw->intelScreen->hw_has_pipelined_register & HW_HAS_PIPELINED_OACONTROL) {
          ctx->Extensions.AMD_performance_monitor = true;
          ctx->Extensions.INTEL_performance_query = true;
       }
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 0a64d2b..36c7bb2 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1275,6 +1275,21 @@ intel_detect_pipelined_so(struct intel_screen *screen)
                                           false);
 }
 
+static bool
+intel_detect_pipelined_oacontrol(struct intel_screen *screen)
+{
+   if (screen->devinfo->gen < 6 || screen->devinfo->gen >= 8)
+      return false;
+
+   /* Set "Select Context ID" to a particular address (which is likely not a
+    * context), but leave all counting disabled.  This should be harmless.
+    */
+   return intel_detect_pipelined_register(screen,
+                                          OACONTROL,
+                                          0x31337000,
+                                          true);
+}
+
 /**
  * Return array of MSAA modes supported by the hardware. The array is
  * zero-terminated and sorted in decreasing order.
@@ -1536,6 +1551,8 @@ __DRIconfig **intelInitScreen2(__DRIscreen *psp)
    intelScreen->hw_has_timestamp = intel_detect_timestamp(intelScreen);
    if (intel_detect_pipelined_so(intelScreen))
       intelScreen->hw_has_pipelined_register |= HW_HAS_PIPELINED_SOL_OFFSET;
+   if (intel_detect_pipelined_oacontrol(intelScreen))
+      intelScreen->hw_has_pipelined_register |= HW_HAS_PIPELINED_OACONTROL;
 
    const char *force_msaa = getenv("INTEL_FORCE_MSAA");
    if (force_msaa) {
diff --git a/src/mesa/drivers/dri/i965/intel_screen.h b/src/mesa/drivers/dri/i965/intel_screen.h
index 7890706..e054b69 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.h
+++ b/src/mesa/drivers/dri/i965/intel_screen.h
@@ -70,7 +70,8 @@ struct intel_screen
     * for each register.
     */
    unsigned hw_has_pipelined_register;
-#define HW_HAS_PIPELINED_SOL_OFFSET (1<<0)
+#define HW_HAS_PIPELINED_SOL_OFFSET     (1<<0)
+#define HW_HAS_PIPELINED_OACONTROL      (1<<1)
 
    dri_bufmgr *bufmgr;
    drm_intel_bo *workaround_bo;
-- 
2.5.0



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