[Mesa-dev] [PATCH 17/70] i965: Rename render_cache dirty tracking to reduce later churn
Chris Wilson
chris at chris-wilson.co.uk
Fri Aug 7 13:13:21 PDT 2015
Simple rename and parameter passing changes now to avoid doing so inside
a much larger patch.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
src/mesa/drivers/dri/i965/brw_batch.h | 5 +++++
src/mesa/drivers/dri/i965/brw_context.c | 3 ++-
src/mesa/drivers/dri/i965/brw_context.h | 2 ++
src/mesa/drivers/dri/i965/brw_draw.c | 6 +++---
src/mesa/drivers/dri/i965/brw_misc_state.c | 8 ++++----
src/mesa/drivers/dri/i965/brw_pipe_control.c | 2 +-
src/mesa/drivers/dri/i965/gen8_depth_state.c | 2 +-
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 2 +-
src/mesa/drivers/dri/i965/intel_fbo.c | 19 ++++++++-----------
src/mesa/drivers/dri/i965/intel_fbo.h | 4 ----
10 files changed, 27 insertions(+), 26 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_batch.h b/src/mesa/drivers/dri/i965/brw_batch.h
index 3b8d354..b9e67dd 100644
--- a/src/mesa/drivers/dri/i965/brw_batch.h
+++ b/src/mesa/drivers/dri/i965/brw_batch.h
@@ -33,6 +33,8 @@ extern "C" {
#include <intel_bufmgr.h>
+#include "util/list.h"
+
typedef drm_intel_bo brw_bo;
enum brw_gpu_ring {
@@ -97,6 +99,9 @@ inline static uint32_t brw_bo_flink(brw_bo *bo)
return name;
}
+void brw_batch_clear_dirty(brw_batch *batch);
+void brw_bo_mark_dirty(brw_batch *batch, brw_bo *bo);
+
#ifdef __cplusplus
}
#endif
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index f8add33..d0c0d23 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -185,7 +185,8 @@ intel_update_state(struct gl_context * ctx, GLuint new_state)
continue;
intel_miptree_all_slices_resolve_depth(brw, tex_obj->mt);
intel_miptree_resolve_color(brw, tex_obj->mt);
- brw_render_cache_set_check_flush(brw, tex_obj->mt->bo);
+ if (brw_check_dirty(brw, tex_obj->mt->bo))
+ brw_emit_mi_flush(brw);
}
_mesa_lock_context_textures(ctx);
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 238d0eb..2c9ac9a 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1993,6 +1993,8 @@ void brw_emit_depth_stall_flushes(struct brw_context *brw);
void gen7_emit_vs_workaround_flush(struct brw_context *brw);
void gen7_emit_cs_stall_flush(struct brw_context *brw);
+bool brw_check_dirty(struct brw_context *ctx, brw_bo *bo);
+
#ifdef __cplusplus
}
#endif
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 1aa0093..8ffc1c5 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -375,12 +375,12 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context *brw)
back_irb->need_downsample = true;
if (depth_irb && ctx->Depth.Mask) {
intel_renderbuffer_att_set_needs_depth_resolve(depth_att);
- brw_render_cache_set_add_bo(brw, depth_irb->mt->bo);
+ brw_bo_mark_dirty(&brw->batch, depth_irb->mt->bo);
}
if (ctx->Extensions.ARB_stencil_texturing &&
stencil_irb && ctx->Stencil._WriteEnabled) {
- brw_render_cache_set_add_bo(brw, stencil_irb->mt->bo);
+ brw_bo_mark_dirty(&brw->batch, stencil_irb->mt->bo);
}
for (int i = 0; i < fb->_NumColorDrawBuffers; i++) {
@@ -388,7 +388,7 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context *brw)
intel_renderbuffer(fb->_ColorDrawBuffers[i]);
if (irb)
- brw_render_cache_set_add_bo(brw, irb->mt->bo);
+ brw_bo_mark_dirty(&brw->batch, irb->mt->bo);
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 122f450..b1e8503 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -546,10 +546,10 @@ brw_emit_depthbuffer(struct brw_context *brw)
height = stencil_irb->Base.Base.Height;
}
- if (depth_mt)
- brw_render_cache_set_check_flush(brw, depth_mt->bo);
- if (stencil_mt)
- brw_render_cache_set_check_flush(brw, stencil_mt->bo);
+ if (depth_mt && brw_check_dirty(brw, depth_mt->bo))
+ brw_emit_mi_flush(brw);
+ if (stencil_mt && brw_check_dirty(brw, stencil_mt->bo))
+ brw_emit_mi_flush(brw);
brw->vtbl.emit_depth_stencil_hiz(brw, depth_mt, depth_offset,
depthbuffer_format, depth_surface_type,
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 1e5a3ba..e513c15 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -326,7 +326,7 @@ brw_emit_mi_flush(struct brw_context *brw)
brw_emit_pipe_control_flush(brw, flags);
}
- brw_render_cache_set_clear(brw);
+ brw_batch_clear_dirty(&brw->batch);
}
void
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index 480eaab..05a003f 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -508,7 +508,7 @@ gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
ADVANCE_BATCH();
/* Mark this buffer as needing a TC flush, as we've rendered to it. */
- brw_render_cache_set_add_bo(brw, mt->bo);
+ brw_bo_mark_dirty(&brw->batch, mt->bo);
/* We've clobbered all of the depth packets, and the drawing rectangle,
* so we need to ensure those packets are re-emitted before the next
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index db9b761..37dcc85 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -59,7 +59,7 @@ intel_batchbuffer_reset(struct brw_context *brw)
brw_bo_put(brw->batch.last_bo);
brw->batch.last_bo = brw->batch.bo;
- brw_render_cache_set_clear(brw);
+ brw_batch_clear_dirty(&brw->batch);
brw->batch.bo = drm_intel_bo_alloc(brw->bufmgr, "batchbuffer",
BATCH_SZ, 4096);
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c
index fbccf7e..5c86655 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -1046,19 +1046,19 @@ intel_renderbuffer_move_to_temp(struct brw_context *brw,
}
void
-brw_render_cache_set_clear(struct brw_context *brw)
+brw_batch_clear_dirty(brw_batch *batch)
{
struct set_entry *entry;
- set_foreach(brw->batch.render_cache, entry) {
- _mesa_set_remove(brw->batch.render_cache, entry);
+ set_foreach(batch->render_cache, entry) {
+ _mesa_set_remove(batch->render_cache, entry);
}
}
void
-brw_render_cache_set_add_bo(struct brw_context *brw, brw_bo *bo)
+brw_bo_mark_dirty(brw_batch *batch, brw_bo *bo)
{
- _mesa_set_add(brw->batch.render_cache, bo);
+ _mesa_set_add(batch->render_cache, bo);
}
/**
@@ -1073,13 +1073,10 @@ brw_render_cache_set_add_bo(struct brw_context *brw, brw_bo *bo)
* necessary is flushed before another use of that BO, but for reuse from
* different caches within a batchbuffer, it's all our responsibility.
*/
-void
-brw_render_cache_set_check_flush(struct brw_context *brw, brw_bo *bo)
+bool
+brw_check_dirty(struct brw_context *brw, brw_bo *bo)
{
- if (!_mesa_set_search(brw->batch.render_cache, bo))
- return;
-
- brw_emit_mi_flush(brw);
+ return _mesa_set_search(brw->batch.render_cache, bo);
}
/**
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.h b/src/mesa/drivers/dri/i965/intel_fbo.h
index aad5bf7..6c761e6 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.h
+++ b/src/mesa/drivers/dri/i965/intel_fbo.h
@@ -240,10 +240,6 @@ void
intel_renderbuffer_upsample(struct brw_context *brw,
struct intel_renderbuffer *irb);
-void brw_render_cache_set_clear(struct brw_context *brw);
-void brw_render_cache_set_add_bo(struct brw_context *brw, brw_bo *bo);
-void brw_render_cache_set_check_flush(struct brw_context *brw, brw_bo *bo);
-
unsigned
intel_quantize_num_samples(struct intel_screen *intel, unsigned num_samples);
--
2.5.0
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