[Mesa-dev] [PATCH 23/70] i965: Refactor adding relocations into the batch buffer
Chris Wilson
chris at chris-wilson.co.uk
Fri Aug 7 13:13:27 PDT 2015
It is essential that the value we write into the batch buffer matches
the value we record in the relocation entry (and that value also
corresponds with the presumed offset the target buffer). To ensure this
is true we combine adding relocation entry to the batch buffer with
recording the target adderss into the state with a convenient helper.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
src/mesa/drivers/dri/i965/brw_batch.h | 22 +++++++
src/mesa/drivers/dri/i965/brw_cc.c | 15 ++---
src/mesa/drivers/dri/i965/brw_clip_state.c | 14 ++---
src/mesa/drivers/dri/i965/brw_context.h | 10 +---
src/mesa/drivers/dri/i965/brw_sampler_state.c | 7 +--
src/mesa/drivers/dri/i965/brw_sf_state.c | 21 +++----
src/mesa/drivers/dri/i965/brw_vs_state.c | 33 ++++-------
src/mesa/drivers/dri/i965/brw_wm_state.c | 38 ++++--------
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 61 ++++++++-----------
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 16 ++---
src/mesa/drivers/dri/i965/gen6_surface_state.c | 12 ++--
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 15 ++---
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 57 ++++++------------
src/mesa/drivers/dri/i965/gen8_surface_state.c | 72 ++++++++---------------
14 files changed, 158 insertions(+), 235 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_batch.h b/src/mesa/drivers/dri/i965/brw_batch.h
index ac64f2f..6c24465 100644
--- a/src/mesa/drivers/dri/i965/brw_batch.h
+++ b/src/mesa/drivers/dri/i965/brw_batch.h
@@ -107,6 +107,28 @@ inline static bool brw_batch_busy(brw_batch *batch)
return batch->last_bo && drm_intel_bo_busy(batch->last_bo);
}
+MUST_CHECK inline static uint64_t
+brw_batch_reloc(brw_batch *batch,
+ uint32_t batch_offset,
+ brw_bo *target_bo,
+ uint64_t target_offset,
+ unsigned read_domains,
+ unsigned write_domain)
+{
+ int ret;
+
+ if (target_bo == NULL)
+ return 0;
+
+ ret = drm_intel_bo_emit_reloc(batch->bo, batch_offset,
+ target_bo, target_offset,
+ read_domains, write_domain);
+ assert(ret == 0);
+ (void)ret;
+
+ return target_bo->offset64 + target_offset;
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/src/mesa/drivers/dri/i965/brw_cc.c b/src/mesa/drivers/dri/i965/brw_cc.c
index 6fa1048..165edec 100644
--- a/src/mesa/drivers/dri/i965/brw_cc.c
+++ b/src/mesa/drivers/dri/i965/brw_cc.c
@@ -226,17 +226,14 @@ static void upload_cc_unit(struct brw_context *brw)
cc->cc5.statistics_enable = 1;
/* BRW_NEW_CC_VP */
- cc->cc4.cc_viewport_state_offset = (brw->batch.bo->offset64 +
- brw->cc.vp_offset) >> 5; /* reloc */
+ cc->cc4.cc_viewport_state_offset =
+ brw_batch_reloc(&brw->batch,
+ (brw->cc.state_offset +
+ offsetof(struct brw_cc_unit_state, cc4)),
+ brw->batch.bo, brw->cc.vp_offset,
+ I915_GEM_DOMAIN_INSTRUCTION, 0) >> 5;
brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
-
- /* Emit CC viewport relocation */
- drm_intel_bo_emit_reloc(brw->batch.bo,
- (brw->cc.state_offset +
- offsetof(struct brw_cc_unit_state, cc4)),
- brw->batch.bo, brw->cc.vp_offset,
- I915_GEM_DOMAIN_INSTRUCTION, 0);
}
const struct brw_tracked_state brw_cc_unit = {
diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c
index dee74db..2ec0c56 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_state.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_state.c
@@ -133,16 +133,14 @@ brw_upload_clip_unit(struct brw_context *brw)
ctx->ViewportArray[0].Width == fb_width &&
ctx->ViewportArray[0].Height == fb_height)
{
+ /* emit clip viewport relocation */
clip->clip5.guard_band_enable = 1;
clip->clip6.clipper_viewport_state_ptr =
- (brw->batch.bo->offset64 + brw->clip.vp_offset) >> 5;
-
- /* emit clip viewport relocation */
- drm_intel_bo_emit_reloc(brw->batch.bo,
- (brw->clip.state_offset +
- offsetof(struct brw_clip_unit_state, clip6)),
- brw->batch.bo, brw->clip.vp_offset,
- I915_GEM_DOMAIN_INSTRUCTION, 0);
+ brw_batch_reloc(&brw->batch,
+ (brw->clip.state_offset +
+ offsetof(struct brw_clip_unit_state, clip6)),
+ brw->batch.bo, brw->clip.vp_offset,
+ I915_GEM_DOMAIN_INSTRUCTION, 0) >> 5;
}
/* _NEW_TRANSFORM */
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index a9bc5e2..31b8c3b 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1880,13 +1880,9 @@ brw_program_reloc(struct brw_context *brw, uint32_t state_offset,
return prog_offset;
}
- drm_intel_bo_emit_reloc(brw->batch.bo,
- state_offset,
- brw->cache.bo,
- prog_offset,
- I915_GEM_DOMAIN_INSTRUCTION, 0);
-
- return brw->cache.bo->offset64 + prog_offset;
+ return brw_batch_reloc(&brw->batch, state_offset,
+ brw->cache.bo, prog_offset,
+ I915_GEM_DOMAIN_INSTRUCTION, 0);
}
bool brw_do_cubemap_normalize(struct exec_list *instructions);
diff --git a/src/mesa/drivers/dri/i965/brw_sampler_state.c b/src/mesa/drivers/dri/i965/brw_sampler_state.c
index 0385806..4531cfa 100644
--- a/src/mesa/drivers/dri/i965/brw_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sampler_state.c
@@ -99,14 +99,13 @@ brw_emit_sampler_state(struct brw_context *brw,
SET_FIELD(mag_filter, BRW_SAMPLER_MAG_FILTER) |
SET_FIELD(min_filter, BRW_SAMPLER_MIN_FILTER);
- ss[2] = border_color_offset;
if (brw->gen < 6) {
- ss[2] += brw->batch.bo->offset64; /* reloc */
- drm_intel_bo_emit_reloc(brw->batch.bo,
+ ss[2] = brw_batch_reloc(&brw->batch,
batch_offset_for_sampler_state + 8,
brw->batch.bo, border_color_offset,
I915_GEM_DOMAIN_SAMPLER, 0);
- }
+ } else
+ ss[2] = border_color_offset;
ss[3] = SET_FIELD(max_anisotropy, BRW_SAMPLER_MAX_ANISOTROPY) |
SET_FIELD(address_rounding, BRW_SAMPLER_ADDRESS_ROUNDING);
diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c
index bab155a..a4a1eb3 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_state.c
@@ -133,7 +133,6 @@ static void upload_sf_unit( struct brw_context *brw )
{
struct gl_context *ctx = &brw->ctx;
struct brw_sf_unit_state *sf;
- brw_bo *bo = brw->batch.bo;
int chipset_max_threads;
bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
@@ -179,9 +178,6 @@ static void upload_sf_unit( struct brw_context *brw )
sf->thread4.stats_enable = 1;
/* BRW_NEW_SF_VP */
- sf->sf5.sf_viewport_state_offset = (brw->batch.bo->offset64 +
- brw->sf.vp_offset) >> 5; /* reloc */
-
sf->sf5.viewport_transform = 1;
/* _NEW_SCISSOR */
@@ -200,6 +196,15 @@ static void upload_sf_unit( struct brw_context *brw )
*/
sf->sf5.front_winding ^= render_to_fbo;
+ sf->sf5.sf_viewport_state_offset =
+ brw_batch_reloc(&brw->batch,
+ (brw->sf.state_offset + offsetof(struct brw_sf_unit_state, sf5)),
+ brw->batch.bo,
+ brw->sf.vp_offset | sf->dw5,
+ I915_GEM_DOMAIN_INSTRUCTION, 0) >> 5;
+
+
+
/* _NEW_POLYGON */
switch (ctx->Polygon.CullFlag ? ctx->Polygon.CullFaceMode : GL_NONE) {
case GL_FRONT:
@@ -291,14 +296,6 @@ static void upload_sf_unit( struct brw_context *brw )
* something loaded through the GPE (L2 ISC), so it's INSTRUCTION domain.
*/
- /* Emit SF viewport relocation */
- drm_intel_bo_emit_reloc(bo, (brw->sf.state_offset +
- offsetof(struct brw_sf_unit_state, sf5)),
- brw->batch.bo, (brw->sf.vp_offset |
- sf->sf5.front_winding |
- (sf->sf5.viewport_transform << 1)),
- I915_GEM_DOMAIN_INSTRUCTION, 0);
-
brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
}
diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c b/src/mesa/drivers/dri/i965/brw_vs_state.c
index b9b97a7..dbef2df 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_state.c
@@ -80,10 +80,16 @@ brw_upload_vs_unit(struct brw_context *brw)
brw->vs.prog_data->base.base.binding_table.size_bytes / 4;
if (brw->vs.prog_data->base.base.total_scratch != 0) {
- vs->thread2.scratch_space_base_pointer =
- stage_state->scratch_bo->offset64 >> 10; /* reloc */
vs->thread2.per_thread_scratch_space =
ffs(brw->vs.prog_data->base.base.total_scratch) - 11;
+
+ vs->thread2.scratch_space_base_pointer =
+ brw_batch_reloc(&brw->batch,
+ stage_state->state_offset + offsetof(struct brw_vs_unit_state, thread2),
+ stage_state->scratch_bo,
+ vs->thread2.per_thread_scratch_space,
+ I915_GEM_DOMAIN_RENDER,
+ I915_GEM_DOMAIN_RENDER) >> 10;
} else {
vs->thread2.scratch_space_base_pointer = 0;
vs->thread2.per_thread_scratch_space = 0;
@@ -158,24 +164,11 @@ brw_upload_vs_unit(struct brw_context *brw)
if (stage_state->sampler_count) {
/* BRW_NEW_SAMPLER_STATE_TABLE - reloc */
vs->vs5.sampler_state_pointer =
- (brw->batch.bo->offset64 + stage_state->sampler_offset) >> 5;
- drm_intel_bo_emit_reloc(brw->batch.bo,
- stage_state->state_offset +
- offsetof(struct brw_vs_unit_state, vs5),
- brw->batch.bo,
- (stage_state->sampler_offset |
- vs->vs5.sampler_count),
- I915_GEM_DOMAIN_INSTRUCTION, 0);
- }
-
- /* Emit scratch space relocation */
- if (brw->vs.prog_data->base.base.total_scratch != 0) {
- drm_intel_bo_emit_reloc(brw->batch.bo,
- stage_state->state_offset +
- offsetof(struct brw_vs_unit_state, thread2),
- stage_state->scratch_bo,
- vs->thread2.per_thread_scratch_space,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
+ brw_batch_reloc(&brw->batch,
+ stage_state->state_offset + offsetof(struct brw_vs_unit_state, vs5),
+ brw->batch.bo,
+ (stage_state->sampler_offset | vs->vs5.sampler_count),
+ I915_GEM_DOMAIN_INSTRUCTION, 0) >> 5;
}
brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index 0cd4390..3b7afde 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -140,10 +140,15 @@ brw_upload_wm_unit(struct brw_context *brw)
prog_data->base.binding_table.size_bytes / 4;
if (prog_data->base.total_scratch != 0) {
- wm->thread2.scratch_space_base_pointer =
- brw->wm.base.scratch_bo->offset64 >> 10; /* reloc */
wm->thread2.per_thread_scratch_space =
ffs(prog_data->base.total_scratch) - 11;
+
+ wm->thread2.scratch_space_base_pointer =
+ brw_batch_reloc(&brw->batch,
+ brw->wm.base.state_offset + offsetof(struct brw_wm_unit_state, thread2),
+ brw->wm.base.scratch_bo,
+ wm->thread2.per_thread_scratch_space,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER) >> 10;
} else {
wm->thread2.scratch_space_base_pointer = 0;
wm->thread2.per_thread_scratch_space = 0;
@@ -167,8 +172,12 @@ brw_upload_wm_unit(struct brw_context *brw)
if (brw->wm.base.sampler_count) {
/* BRW_NEW_SAMPLER_STATE_TABLE - reloc */
- wm->wm4.sampler_state_pointer = (brw->batch.bo->offset64 +
- brw->wm.base.sampler_offset) >> 5;
+ wm->wm4.sampler_state_pointer =
+ brw_batch_reloc(&brw->batch,
+ brw->wm.base.state_offset + offsetof(struct brw_wm_unit_state, wm4),
+ brw->batch.bo,
+ brw->wm.base.sampler_offset | wm->dw4,
+ I915_GEM_DOMAIN_INSTRUCTION, 0) >> 5;
} else {
wm->wm4.sampler_state_pointer = 0;
}
@@ -229,27 +238,6 @@ brw_upload_wm_unit(struct brw_context *brw)
if (unlikely(INTEL_DEBUG & DEBUG_STATS) || brw->stats_wm)
wm->wm4.stats_enable = 1;
- /* Emit scratch space relocation */
- if (prog_data->base.total_scratch != 0) {
- drm_intel_bo_emit_reloc(brw->batch.bo,
- brw->wm.base.state_offset +
- offsetof(struct brw_wm_unit_state, thread2),
- brw->wm.base.scratch_bo,
- wm->thread2.per_thread_scratch_space,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
- }
-
- /* Emit sampler state relocation */
- if (brw->wm.base.sampler_count != 0) {
- drm_intel_bo_emit_reloc(brw->batch.bo,
- brw->wm.base.state_offset +
- offsetof(struct brw_wm_unit_state, wm4),
- brw->batch.bo, (brw->wm.base.sampler_offset |
- wm->wm4.stats_enable |
- (wm->wm4.sampler_count << 2)),
- I915_GEM_DOMAIN_INSTRUCTION, 0);
- }
-
brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 60f2aa6..53d225e 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -256,7 +256,10 @@ gen4_emit_buffer_surface_state(struct brw_context *brw,
surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
surface_format << BRW_SURFACE_FORMAT_SHIFT |
(brw->gen >= 6 ? BRW_SURFACE_RC_READ_WRITE : 0);
- surf[1] = (bo ? bo->offset64 : 0) + buffer_offset; /* reloc */
+ surf[1] = brw_batch_reloc(&brw->batch, *out_offset + 4,
+ bo, buffer_offset,
+ I915_GEM_DOMAIN_SAMPLER,
+ (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
surf[2] = (buffer_size & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
((buffer_size >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT;
surf[3] = ((buffer_size >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
@@ -267,10 +270,6 @@ gen4_emit_buffer_surface_state(struct brw_context *brw,
* physical cache. It is mapped in hardware to the sampler cache."
*/
if (bo) {
- drm_intel_bo_emit_reloc(brw->batch.bo, *out_offset + 4,
- bo, buffer_offset,
- I915_GEM_DOMAIN_SAMPLER,
- (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
}
}
@@ -366,7 +365,11 @@ brw_update_texture_surface(struct gl_context *ctx,
BRW_SURFACE_CUBEFACE_ENABLES |
tex_format << BRW_SURFACE_FORMAT_SHIFT);
- surf[1] = mt->bo->offset64 + mt->offset; /* reloc */
+ surf[1] = brw_batch_reloc(&brw->batch,
+ *surf_offset + 4,
+ mt->bo,
+ mt->offset,
+ I915_GEM_DOMAIN_SAMPLER, 0);
surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
(mt->logical_width0 - 1) << BRW_SURFACE_WIDTH_SHIFT |
@@ -380,13 +383,6 @@ brw_update_texture_surface(struct gl_context *ctx,
SET_FIELD(tObj->BaseLevel - mt->first_level, BRW_SURFACE_MIN_LOD));
surf[5] = mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
-
- /* Emit relocation to surface contents */
- drm_intel_bo_emit_reloc(brw->batch.bo,
- *surf_offset + 4,
- mt->bo,
- surf[1] - mt->bo->offset64,
- I915_GEM_DOMAIN_SAMPLER, 0);
}
/**
@@ -479,19 +475,17 @@ brw_update_sol_surface(struct brw_context *brw,
BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
surface_format << BRW_SURFACE_FORMAT_SHIFT |
BRW_SURFACE_RC_READ_WRITE;
- surf[1] = bo->offset64 + offset_bytes; /* reloc */
+ surf[1] = brw_batch_reloc(&brw->batch,
+ *out_offset + 4,
+ bo, offset_bytes,
+ I915_GEM_DOMAIN_RENDER,
+ I915_GEM_DOMAIN_RENDER);
surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT |
height << BRW_SURFACE_HEIGHT_SHIFT);
surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT |
pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
surf[4] = 0;
surf[5] = 0;
-
- /* Emit relocation to surface contents. */
- drm_intel_bo_emit_reloc(brw->batch.bo,
- *out_offset + 4,
- bo, offset_bytes,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
}
/* Creates a new WM constant buffer reflecting the current fragment program's
@@ -599,7 +593,10 @@ brw_emit_null_surface_state(struct brw_context *brw,
1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT |
1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
}
- surf[1] = bo ? bo->offset64 : 0;
+ surf[1] = brw_batch_reloc(&brw->batch, *out_offset + 4,
+ bo, 0,
+ I915_GEM_DOMAIN_RENDER,
+ I915_GEM_DOMAIN_RENDER);
surf[2] = ((width - 1) << BRW_SURFACE_WIDTH_SHIFT |
(height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
@@ -612,13 +609,6 @@ brw_emit_null_surface_state(struct brw_context *brw,
pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
surf[4] = multisampling_state;
surf[5] = 0;
-
- if (bo) {
- drm_intel_bo_emit_reloc(brw->batch.bo,
- *out_offset + 4,
- bo, 0,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
- }
}
/**
@@ -675,8 +665,12 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
/* reloc */
assert(mt->offset % mt->cpp == 0);
- surf[1] = (intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y) +
- mt->bo->offset64 + mt->offset);
+ surf[1] = brw_batch_reloc(&brw->batch, offset + 4,
+ mt->bo,
+ mt->offset +
+ intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y),
+ I915_GEM_DOMAIN_RENDER,
+ I915_GEM_DOMAIN_RENDER);
surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
(rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
@@ -718,13 +712,6 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
}
}
- drm_intel_bo_emit_reloc(brw->batch.bo,
- offset + 4,
- mt->bo,
- surf[1] - mt->bo->offset64,
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER);
-
return offset;
}
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 8154bc1..a46c2e9 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -385,9 +385,12 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
BRW_SURFACE_CUBEFACE_ENABLES |
surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT);
- /* reloc */
- surf[1] = (surface->compute_tile_offsets(&tile_x, &tile_y) +
- mt->bo->offset64);
+ surf[1] = brw_batch_reloc(&brw->batch,
+ wm_surf_offset + 4,
+ mt->bo,
+ surface->compute_tile_offsets(&tile_x, &tile_y),
+ read_domains, write_domain);
+
surf[2] = (0 << BRW_SURFACE_LOD_SHIFT |
(width - 1) << BRW_SURFACE_WIDTH_SHIFT |
@@ -415,13 +418,6 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
(surface->mt->align_h == 4 ?
BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
- /* Emit relocation to surface contents */
- drm_intel_bo_emit_reloc(brw->batch.bo,
- wm_surf_offset + 4,
- mt->bo,
- surf[1] - mt->bo->offset64,
- read_domains, write_domain);
-
return wm_surf_offset;
}
diff --git a/src/mesa/drivers/dri/i965/gen6_surface_state.c b/src/mesa/drivers/dri/i965/gen6_surface_state.c
index ba3980d..793bbbb 100644
--- a/src/mesa/drivers/dri/i965/gen6_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_surface_state.c
@@ -95,7 +95,10 @@ gen6_update_renderbuffer_surface(struct brw_context *brw,
/* reloc */
assert(mt->offset % mt->cpp == 0);
- surf[1] = mt->bo->offset64 + mt->offset;
+ surf[1] = brw_batch_reloc(&brw->batch, offset + 4,
+ mt->bo, mt->offset,
+ I915_GEM_DOMAIN_RENDER,
+ I915_GEM_DOMAIN_RENDER);
/* In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1
* (Surface Arrays For all surfaces other than separate stencil buffer):
@@ -127,13 +130,6 @@ gen6_update_renderbuffer_surface(struct brw_context *brw,
surf[5] = (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0);
- drm_intel_bo_emit_reloc(brw->batch.bo,
- offset + 4,
- mt->bo,
- surf[1] - mt->bo->offset64,
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER);
-
return offset;
}
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 4fa97e5..3f6ac6d 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -167,9 +167,11 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
else
surf[0] |= GEN7_SURFACE_ARYSPC_FULL;
- /* reloc */
- surf[1] =
- surface->compute_tile_offsets(&tile_x, &tile_y) + mt->bo->offset64;
+ surf[1] = brw_batch_reloc(&brw->batch,
+ wm_surf_offset + 4,
+ mt->bo,
+ surface->compute_tile_offsets(&tile_x, &tile_y),
+ read_domains, write_domain);
/* Note that the low bits of these fields are missing, so
* there's the possibility of getting in trouble.
@@ -203,13 +205,6 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
}
- /* Emit relocation to surface contents */
- drm_intel_bo_emit_reloc(brw->batch.bo,
- wm_surf_offset + 4,
- mt->bo,
- surf[1] - mt->bo->offset64,
- read_domains, write_domain);
-
gen7_check_surface_setup(surf, is_render_target);
return wm_surf_offset;
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 1885aed..45aa536 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -115,19 +115,14 @@ gen7_set_surface_mcs_info(struct brw_context *brw,
* thus have their lower 12 bits zero), we can use an ordinary reloc to do
* the necessary address translation.
*/
- assert ((mcs_mt->bo->offset64 & 0xfff) == 0);
-
- surf[6] = GEN7_SURFACE_MCS_ENABLE |
- SET_FIELD(pitch_tiles - 1, GEN7_SURFACE_MCS_PITCH) |
- mcs_mt->bo->offset64;
-
- drm_intel_bo_emit_reloc(brw->batch.bo,
- surf_offset + 6 * 4,
- mcs_mt->bo,
- surf[6] & 0xfff,
- is_render_target ? I915_GEM_DOMAIN_RENDER
- : I915_GEM_DOMAIN_SAMPLER,
- is_render_target ? I915_GEM_DOMAIN_RENDER : 0);
+ surf[6] = brw_batch_reloc(&brw->batch,
+ surf_offset + 6 * 4,
+ mcs_mt->bo,
+ GEN7_SURFACE_MCS_ENABLE |
+ SET_FIELD(pitch_tiles - 1, GEN7_SURFACE_MCS_PITCH),
+ is_render_target ? I915_GEM_DOMAIN_RENDER
+ : I915_GEM_DOMAIN_SAMPLER,
+ is_render_target ? I915_GEM_DOMAIN_RENDER : 0);
}
@@ -234,7 +229,9 @@ gen7_emit_buffer_surface_state(struct brw_context *brw,
surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
surface_format << BRW_SURFACE_FORMAT_SHIFT |
BRW_SURFACE_RC_READ_WRITE;
- surf[1] = (bo ? bo->offset64 : 0) + buffer_offset; /* reloc */
+ surf[1] = brw_batch_reloc(&brw->batch, *out_offset + 4,
+ bo, buffer_offset, I915_GEM_DOMAIN_SAMPLER,
+ (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
surf[2] = SET_FIELD((buffer_size - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
SET_FIELD(((buffer_size - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
if (surface_format == BRW_SURFACEFORMAT_RAW)
@@ -252,13 +249,6 @@ gen7_emit_buffer_surface_state(struct brw_context *brw,
SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
}
- /* Emit relocation to surface contents */
- if (bo) {
- drm_intel_bo_emit_reloc(brw->batch.bo, *out_offset + 4,
- bo, buffer_offset, I915_GEM_DOMAIN_SAMPLER,
- (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
- }
-
gen7_check_surface_setup(surf, false /* is_render_target */);
}
@@ -298,7 +288,10 @@ gen7_emit_texture_surface_state(struct brw_context *brw,
if (mt->array_layout == ALL_SLICES_AT_EACH_LOD)
surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
- surf[1] = mt->bo->offset64 + mt->offset; /* reloc */
+ surf[1] = brw_batch_reloc(&brw->batch, *surf_offset + 4,
+ mt->bo, mt->offset,
+ I915_GEM_DOMAIN_SAMPLER,
+ (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
@@ -335,14 +328,6 @@ gen7_emit_texture_surface_state(struct brw_context *brw,
mt->mcs_mt, false /* is RT */);
}
- /* Emit relocation to surface contents */
- drm_intel_bo_emit_reloc(brw->batch.bo,
- *surf_offset + 4,
- mt->bo,
- surf[1] - mt->bo->offset64,
- I915_GEM_DOMAIN_SAMPLER,
- (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
-
gen7_check_surface_setup(surf, false /* is_render_target */);
}
@@ -518,7 +503,10 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
}
assert(mt->offset % mt->cpp == 0);
- surf[1] = mt->bo->offset64 + mt->offset;
+ surf[1] = brw_batch_reloc(&brw->batch, offset + 4,
+ mt->bo, mt->offset,
+ I915_GEM_DOMAIN_RENDER,
+ I915_GEM_DOMAIN_RENDER);
assert(brw->has_surface_tile_offset);
@@ -549,13 +537,6 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
}
- drm_intel_bo_emit_reloc(brw->batch.bo,
- offset + 4,
- mt->bo,
- surf[1] - mt->bo->offset64,
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER);
-
gen7_check_surface_setup(surf, true /* is_render_target */);
return offset;
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index e6cd503..52e24e8 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -170,15 +170,11 @@ gen8_emit_buffer_surface_state(struct brw_context *brw,
SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) |
SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
- /* reloc */
- *((uint64_t *) &surf[8]) = (bo ? bo->offset64 : 0) + buffer_offset;
-
/* Emit relocation to surface contents. */
- if (bo) {
- drm_intel_bo_emit_reloc(brw->batch.bo, *out_offset + 8 * 4,
- bo, buffer_offset, I915_GEM_DOMAIN_SAMPLER,
- rw ? I915_GEM_DOMAIN_SAMPLER : 0);
- }
+ *((uint64_t *)&surf[8]) =
+ brw_batch_reloc(&brw->batch, *out_offset + 8 * 4,
+ bo, buffer_offset, I915_GEM_DOMAIN_SAMPLER,
+ rw ? I915_GEM_DOMAIN_SAMPLER : 0);
}
static void
@@ -274,27 +270,18 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 2)), GEN7_SURFACE_SCS_B) |
SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 3)), GEN7_SURFACE_SCS_A);
- *((uint64_t *) &surf[8]) = mt->bo->offset64 + mt->offset; /* reloc */
-
- if (aux_mt) {
- *((uint64_t *) &surf[10]) = aux_mt->bo->offset64;
- drm_intel_bo_emit_reloc(brw->batch.bo, *surf_offset + 10 * 4,
- aux_mt->bo, 0,
- I915_GEM_DOMAIN_SAMPLER,
- (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
- } else {
- surf[10] = 0;
- surf[11] = 0;
- }
+ *((uint64_t *)&surf[8]) =
+ brw_batch_reloc(&brw->batch, *surf_offset + 8 * 4,
+ mt->bo, mt->offset,
+ I915_GEM_DOMAIN_SAMPLER,
+ (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
+
+ *((uint64_t *)&surf[10]) =
+ brw_batch_reloc(&brw->batch, *surf_offset + 10 * 4,
+ aux_mt ? aux_mt->bo : NULL, 0,
+ I915_GEM_DOMAIN_SAMPLER,
+ (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
surf[12] = 0;
-
- /* Emit relocation to surface contents */
- drm_intel_bo_emit_reloc(brw->batch.bo,
- *surf_offset + 8 * 4,
- mt->bo,
- mt->offset,
- I915_GEM_DOMAIN_SAMPLER,
- (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
}
static void
@@ -500,27 +487,18 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
assert(mt->offset % mt->cpp == 0);
- *((uint64_t *) &surf[8]) = mt->bo->offset64 + mt->offset; /* reloc */
-
- if (aux_mt) {
- *((uint64_t *) &surf[10]) = aux_mt->bo->offset64;
- drm_intel_bo_emit_reloc(brw->batch.bo,
- offset + 10 * 4,
- aux_mt->bo, 0,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
- } else {
- surf[10] = 0;
- surf[11] = 0;
- }
+ *((uint64_t *) &surf[8]) =
+ brw_batch_reloc(&brw->batch, offset + 8*4,
+ mt->bo, mt->offset,
+ I915_GEM_DOMAIN_RENDER,
+ I915_GEM_DOMAIN_RENDER);
+
+ *((uint64_t *)&surf[10]) =
+ brw_batch_reloc(&brw->batch, offset + 10 * 4,
+ aux_mt ? aux_mt->bo : NULL, 0,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
surf[12] = 0;
- drm_intel_bo_emit_reloc(brw->batch.bo,
- offset + 8 * 4,
- mt->bo,
- mt->offset,
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER);
-
return offset;
}
--
2.5.0
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