[Mesa-dev] [PATCH 25/70] i965: Move bufmgr from brw_context to brw_batch
Chris Wilson
chris at chris-wilson.co.uk
Fri Aug 7 13:13:29 PDT 2015
Since brw_batch will become the dominate interface for brw_bo, move the
pointer now to reduce later churn.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
src/mesa/drivers/dri/i965/brw_batch.h | 2 ++
src/mesa/drivers/dri/i965/brw_binding_tables.c | 2 +-
src/mesa/drivers/dri/i965/brw_context.c | 8 ++++----
src/mesa/drivers/dri/i965/brw_context.h | 6 ++----
src/mesa/drivers/dri/i965/brw_performance_monitor.c | 6 +++---
src/mesa/drivers/dri/i965/brw_program.c | 4 ++--
src/mesa/drivers/dri/i965/brw_queryobj.c | 16 ++++++++--------
src/mesa/drivers/dri/i965/brw_state_cache.c | 4 ++--
src/mesa/drivers/dri/i965/gen6_queryobj.c | 2 +-
src/mesa/drivers/dri/i965/gen6_sol.c | 4 ++--
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 2 +-
src/mesa/drivers/dri/i965/intel_buffer_objects.c | 6 +++---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 10 +++++-----
src/mesa/drivers/dri/i965/intel_upload.c | 2 +-
14 files changed, 37 insertions(+), 37 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_batch.h b/src/mesa/drivers/dri/i965/brw_batch.h
index 6c24465..9e2d7fa 100644
--- a/src/mesa/drivers/dri/i965/brw_batch.h
+++ b/src/mesa/drivers/dri/i965/brw_batch.h
@@ -67,6 +67,8 @@ typedef struct brw_batch {
int reloc_count;
} saved;
+ dri_bufmgr *bufmgr;
+
/**
* Set of brw_bo* that have been rendered to within this batchbuffer
* and would need flushing before being used from another cache domain that
diff --git a/src/mesa/drivers/dri/i965/brw_binding_tables.c b/src/mesa/drivers/dri/i965/brw_binding_tables.c
index 9fe4bc8..c03dc59 100644
--- a/src/mesa/drivers/dri/i965/brw_binding_tables.c
+++ b/src/mesa/drivers/dri/i965/brw_binding_tables.c
@@ -328,7 +328,7 @@ gen7_enable_hw_binding_tables(struct brw_context *brw)
* "A maximum of 16,383 Binding tables are allowed in any batch buffer"
*/
static const int max_size = 16383 * 4;
- brw->hw_bt_pool.bo = drm_intel_bo_alloc(brw->bufmgr, "hw_bt",
+ brw->hw_bt_pool.bo = drm_intel_bo_alloc(brw->batch.bufmgr, "hw_bt",
max_size, 64);
brw->hw_bt_pool.next_offset = 0;
}
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 707bdf2..971d86d 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -628,7 +628,7 @@ brw_process_driconf_options(struct brw_context *brw)
case DRI_CONF_BO_REUSE_DISABLED:
break;
case DRI_CONF_BO_REUSE_ALL:
- intel_bufmgr_gem_enable_reuse(brw->bufmgr);
+ intel_bufmgr_gem_enable_reuse(brw->intelScreen->bufmgr);
break;
}
@@ -707,7 +707,7 @@ brwCreateContext(gl_api api,
driContextPriv->driverPrivate = brw;
brw->driContext = driContextPriv;
brw->intelScreen = screen;
- brw->bufmgr = screen->bufmgr;
+ brw->batch.bufmgr = screen->bufmgr;
brw->gen = devinfo->gen;
brw->gt = devinfo->gt;
@@ -812,7 +812,7 @@ brwCreateContext(gl_api api,
* This is required for transform feedback buffer offsets, query objects,
* and also allows us to reduce how much state we have to emit.
*/
- brw->hw_ctx = drm_intel_gem_context_create(brw->bufmgr);
+ brw->hw_ctx = drm_intel_gem_context_create(brw->batch.bufmgr);
if (!brw->hw_ctx) {
fprintf(stderr, "Gen6+ requires Kernel 3.6 or later.\n");
@@ -1377,7 +1377,7 @@ intel_process_dri2_buffer(struct brw_context *brw,
buffer->cpp, buffer->pitch);
}
- bo = drm_intel_bo_gem_create_from_name(brw->bufmgr, buffer_name,
+ bo = drm_intel_bo_gem_create_from_name(brw->batch.bufmgr, buffer_name,
buffer->name);
if (!bo) {
fprintf(stderr,
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 31b8c3b..6301da4 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1000,7 +1000,8 @@ struct brw_context
} vtbl;
- dri_bufmgr *bufmgr;
+ brw_batch batch;
+ bool no_batch_wrap;
drm_intel_context *hw_ctx;
@@ -1016,9 +1017,6 @@ struct brw_context
*/
uint32_t reset_count;
- brw_batch batch;
- bool no_batch_wrap;
-
struct {
brw_bo *bo;
uint32_t next_offset;
diff --git a/src/mesa/drivers/dri/i965/brw_performance_monitor.c b/src/mesa/drivers/dri/i965/brw_performance_monitor.c
index b92b1d7..4795861 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_monitor.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_monitor.c
@@ -1101,13 +1101,13 @@ brw_begin_perf_monitor(struct gl_context *ctx,
* wasting memory for contexts that don't use performance monitors.
*/
if (!brw->perfmon.bookend_bo) {
- brw->perfmon.bookend_bo = drm_intel_bo_alloc(brw->bufmgr,
+ brw->perfmon.bookend_bo = drm_intel_bo_alloc(brw->batch.bufmgr,
"OA bookend BO",
BOOKEND_BO_SIZE_BYTES, 64);
}
monitor->oa_bo =
- drm_intel_bo_alloc(brw->bufmgr, "perf. monitor OA bo", 4096, 64);
+ drm_intel_bo_alloc(brw->batch.bufmgr, "perf. monitor OA bo", 4096, 64);
#ifdef DEBUG
/* Pre-filling the BO helps debug whether writes landed. */
drm_intel_bo_map(monitor->oa_bo, true);
@@ -1142,7 +1142,7 @@ brw_begin_perf_monitor(struct gl_context *ctx,
if (monitor_needs_statistics_registers(brw, m)) {
monitor->pipeline_stats_bo =
- drm_intel_bo_alloc(brw->bufmgr, "perf. monitor stats bo", 4096, 64);
+ drm_intel_bo_alloc(brw->batch.bufmgr, "perf. monitor stats bo", 4096, 64);
/* Take starting snapshots. */
snapshot_statistics_registers(brw, monitor, 0);
diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
index 7dc3e8c..687bc46 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -271,7 +271,7 @@ brw_get_scratch_bo(struct brw_context *brw,
}
if (!old_bo) {
- *scratch_bo = drm_intel_bo_alloc(brw->bufmgr, "scratch bo", size, 4096);
+ *scratch_bo = drm_intel_bo_alloc(brw->batch.bufmgr, "scratch bo", size, 4096);
}
}
@@ -300,7 +300,7 @@ brw_init_shader_time(struct brw_context *brw)
{
const int max_entries = 2048;
brw->shader_time.bo =
- drm_intel_bo_alloc(brw->bufmgr, "shader time",
+ drm_intel_bo_alloc(brw->batch.bufmgr, "shader time",
max_entries * SHADER_TIME_STRIDE * 3, 4096);
brw->shader_time.names = rzalloc_array(brw, const char *, max_entries);
brw->shader_time.ids = rzalloc_array(brw, int, max_entries);
diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c
index 344993e..6f29d04 100644
--- a/src/mesa/drivers/dri/i965/brw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/brw_queryobj.c
@@ -236,7 +236,7 @@ brw_begin_query(struct gl_context *ctx, struct gl_query_object *q)
* the system was doing other work, such as running other applications.
*/
brw_bo_put(query->bo);
- query->bo = drm_intel_bo_alloc(brw->bufmgr, "timer query", 4096, 4096);
+ query->bo = drm_intel_bo_alloc(brw->batch.bufmgr, "timer query", 4096, 4096);
brw_write_timestamp(brw, query->bo, 0);
break;
@@ -394,7 +394,7 @@ ensure_bo_has_space(struct gl_context *ctx, struct brw_query_object *query)
brw_queryobj_get_results(ctx, query);
}
- query->bo = drm_intel_bo_alloc(brw->bufmgr, "query", 4096, 1);
+ query->bo = drm_intel_bo_alloc(brw->batch.bufmgr, "query", 4096, 1);
query->last_index = 0;
}
}
@@ -480,7 +480,7 @@ brw_query_counter(struct gl_context *ctx, struct gl_query_object *q)
assert(q->Target == GL_TIMESTAMP);
brw_bo_put(query->bo);
- query->bo = drm_intel_bo_alloc(brw->bufmgr, "timestamp query", 4096, 4096);
+ query->bo = drm_intel_bo_alloc(brw->batch.bufmgr, "timestamp query", 4096, 4096);
brw_write_timestamp(brw, query->bo, 0);
query->flushed = false;
@@ -494,19 +494,19 @@ brw_query_counter(struct gl_context *ctx, struct gl_query_object *q)
static uint64_t
brw_get_timestamp(struct gl_context *ctx)
{
- struct brw_context *brw = brw_context(ctx);
+ struct intel_screen *screen = brw_context(ctx)->intelScreen;
uint64_t result = 0;
- switch (brw->intelScreen->hw_has_timestamp) {
+ switch (screen->hw_has_timestamp) {
case 3: /* New kernel, always full 36bit accuracy */
- drm_intel_reg_read(brw->bufmgr, TIMESTAMP | 1, &result);
+ drm_intel_reg_read(screen->bufmgr, TIMESTAMP | 1, &result);
break;
case 2: /* 64bit kernel, result is left-shifted by 32bits, losing 4bits */
- drm_intel_reg_read(brw->bufmgr, TIMESTAMP, &result);
+ drm_intel_reg_read(screen->bufmgr, TIMESTAMP, &result);
result = result >> 32;
break;
case 1: /* 32bit kernel, result is 36bit wide but may be inaccurate! */
- drm_intel_reg_read(brw->bufmgr, TIMESTAMP, &result);
+ drm_intel_reg_read(screen->bufmgr, TIMESTAMP, &result);
break;
}
diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c b/src/mesa/drivers/dri/i965/brw_state_cache.c
index 48db407..0081219 100644
--- a/src/mesa/drivers/dri/i965/brw_state_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_state_cache.c
@@ -170,7 +170,7 @@ brw_cache_new_bo(struct brw_cache *cache, uint32_t new_size)
struct brw_context *brw = cache->brw;
brw_bo *new_bo;
- new_bo = drm_intel_bo_alloc(brw->bufmgr, "program cache", new_size, 64);
+ new_bo = drm_intel_bo_alloc(brw->batch.bufmgr, "program cache", new_size, 64);
if (brw->has_llc)
drm_intel_gem_bo_map_unsynchronized(new_bo);
@@ -354,7 +354,7 @@ brw_init_caches(struct brw_context *brw)
cache->items =
calloc(cache->size, sizeof(struct brw_cache_item *));
- cache->bo = drm_intel_bo_alloc(brw->bufmgr,
+ cache->bo = drm_intel_bo_alloc(brw->batch.bufmgr,
"program cache",
4096, 64);
if (brw->has_llc)
diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c b/src/mesa/drivers/dri/i965/gen6_queryobj.c
index b9269de..2178ca5 100644
--- a/src/mesa/drivers/dri/i965/gen6_queryobj.c
+++ b/src/mesa/drivers/dri/i965/gen6_queryobj.c
@@ -279,7 +279,7 @@ gen6_begin_query(struct gl_context *ctx, struct gl_query_object *q)
/* Since we're starting a new query, we need to throw away old results. */
brw_bo_put(query->bo);
- query->bo = drm_intel_bo_alloc(brw->bufmgr, "query results", 4096, 4096);
+ query->bo = drm_intel_bo_alloc(brw->batch.bufmgr, "query results", 4096, 4096);
switch (query->Base.Target) {
case GL_TIME_ELAPSED:
diff --git a/src/mesa/drivers/dri/i965/gen6_sol.c b/src/mesa/drivers/dri/i965/gen6_sol.c
index 47a18a1..22f350f 100644
--- a/src/mesa/drivers/dri/i965/gen6_sol.c
+++ b/src/mesa/drivers/dri/i965/gen6_sol.c
@@ -204,9 +204,9 @@ brw_new_transform_feedback(struct gl_context *ctx, GLuint name)
_mesa_init_transform_feedback_object(&brw_obj->base, name);
brw_obj->offset_bo =
- drm_intel_bo_alloc(brw->bufmgr, "transform feedback offsets", 16, 64);
+ drm_intel_bo_alloc(brw->batch.bufmgr, "transform feedback offsets", 16, 64);
brw_obj->prim_count_bo =
- drm_intel_bo_alloc(brw->bufmgr, "xfb primitive counts", 4096, 64);
+ drm_intel_bo_alloc(brw->batch.bufmgr, "xfb primitive counts", 4096, 64);
return &brw_obj->base;
}
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 32b409a..712eee0 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -61,7 +61,7 @@ intel_batchbuffer_reset(struct brw_context *brw)
brw_batch_clear_dirty(&brw->batch);
- brw->batch.bo = drm_intel_bo_alloc(brw->bufmgr, "batchbuffer",
+ brw->batch.bo = drm_intel_bo_alloc(brw->batch.bufmgr, "batchbuffer",
BATCH_SZ, 4096);
if (brw->has_llc) {
drm_intel_bo_map(brw->batch.bo, true);
diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
index be2c66b..b9a36f2 100644
--- a/src/mesa/drivers/dri/i965/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
@@ -100,7 +100,7 @@ static void
alloc_buffer_object(struct brw_context *brw,
struct intel_buffer_object *intel_obj)
{
- intel_obj->buffer = drm_intel_bo_alloc(brw->bufmgr, "bufferobj",
+ intel_obj->buffer = drm_intel_bo_alloc(brw->batch.bufmgr, "bufferobj",
intel_obj->Base.Size, 64);
/* the buffer might be bound as a uniform buffer, need to update it
@@ -285,7 +285,7 @@ brw_buffer_subdata(struct gl_context *ctx,
intel_obj->gpu_active_start,
intel_obj->gpu_active_end);
brw_bo *temp_bo =
- drm_intel_bo_alloc(brw->bufmgr, "subdata temp", size, 64);
+ drm_intel_bo_alloc(brw->batch.bufmgr, "subdata temp", size, 64);
drm_intel_bo_subdata(temp_bo, 0, size, data);
@@ -422,7 +422,7 @@ brw_map_buffer_range(struct gl_context *ctx,
const unsigned alignment = ctx->Const.MinMapBufferAlignment;
intel_obj->map_extra[index] = (uintptr_t) offset % alignment;
- intel_obj->range_map_bo[index] = drm_intel_bo_alloc(brw->bufmgr,
+ intel_obj->range_map_bo[index] = drm_intel_bo_alloc(brw->batch.bufmgr,
"BO blit temp",
length +
intel_obj->map_extra[index],
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 174649b..86aacfb 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -668,10 +668,10 @@ intel_miptree_create(struct brw_context *brw,
unsigned long size;
size = intel_get_yf_ys_bo_size(mt, &alignment, &pitch);
assert(size);
- mt->bo = drm_intel_bo_alloc_for_render(brw->bufmgr, "miptree",
+ mt->bo = drm_intel_bo_alloc_for_render(brw->batch.bufmgr, "miptree",
size, alignment);
} else {
- mt->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "miptree",
+ mt->bo = drm_intel_bo_alloc_tiled(brw->batch.bufmgr, "miptree",
total_width, total_height, mt->cpp,
&mt->tiling, &pitch,
alloc_flags);
@@ -689,7 +689,7 @@ intel_miptree_create(struct brw_context *brw,
mt->tiling = I915_TILING_X;
brw_bo_put(mt->bo);
- mt->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "miptree",
+ mt->bo = drm_intel_bo_alloc_tiled(brw->batch.bufmgr, "miptree",
total_width, total_height, mt->cpp,
&mt->tiling, &pitch, alloc_flags);
mt->pitch = pitch;
@@ -1572,7 +1572,7 @@ intel_gen7_hiz_buf_create(struct brw_context *brw,
unsigned long pitch;
uint32_t tiling = I915_TILING_Y;
- buf->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "hiz",
+ buf->bo = drm_intel_bo_alloc_tiled(brw->batch.bufmgr, "hiz",
hz_width, hz_height, 1,
&tiling, &pitch,
BO_ALLOC_FOR_RENDER);
@@ -1675,7 +1675,7 @@ intel_gen8_hiz_buf_create(struct brw_context *brw,
unsigned long pitch;
uint32_t tiling = I915_TILING_Y;
- buf->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "hiz",
+ buf->bo = drm_intel_bo_alloc_tiled(brw->batch.bufmgr, "hiz",
hz_width, hz_height, 1,
&tiling, &pitch,
BO_ALLOC_FOR_RENDER);
diff --git a/src/mesa/drivers/dri/i965/intel_upload.c b/src/mesa/drivers/dri/i965/intel_upload.c
index f489b77..4ec7e05 100644
--- a/src/mesa/drivers/dri/i965/intel_upload.c
+++ b/src/mesa/drivers/dri/i965/intel_upload.c
@@ -100,7 +100,7 @@ intel_upload_space(struct brw_context *brw,
}
if (!brw->upload.bo) {
- brw->upload.bo = drm_intel_bo_alloc(brw->bufmgr, "streamed data",
+ brw->upload.bo = drm_intel_bo_alloc(brw->batch.bufmgr, "streamed data",
MAX2(INTEL_UPLOAD_SIZE, size), 4096);
if (brw->has_llc)
drm_intel_bo_map(brw->upload.bo, true);
--
2.5.0
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