[Mesa-dev] [PATCH 38/70] i965: Move a few intel_batchbuffer functions to brw_batch

[Chris Wilson]

In preparation for the next patch, just transplant some functions
between header files.

Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
 src/mesa/drivers/dri/i965/brw_batch.h         | 41 +++++++++++++++++++++++++++
 src/mesa/drivers/dri/i965/intel_batchbuffer.h | 40 --------------------------
 2 files changed, 41 insertions(+), 40 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_batch.h b/src/mesa/drivers/dri/i965/brw_batch.h
index 3baaba9..4a50e1b 100644
--- a/src/mesa/drivers/dri/i965/brw_batch.h
+++ b/src/mesa/drivers/dri/i965/brw_batch.h
@@ -221,6 +221,47 @@ inline static void brw_batch_maybe_flush(struct brw_batch *batch)
       brw_batch_flush(batch, NULL);
 }
 
+void intel_batchbuffer_save_state(struct brw_batch *batch);
+void intel_batchbuffer_reset_to_saved(struct brw_batch *batch);
+
+void intel_batchbuffer_emit_render_ring_prelude(struct brw_batch *batch);
+
+#define USED_BATCH(batch) ((uintptr_t)((batch)->map_next - (batch)->map))
+
+static inline unsigned
+intel_batchbuffer_space(struct brw_batch *batch)
+{
+   return (batch->state_batch_offset - batch->reserved_space)
+      - USED_BATCH(batch)*4;
+}
+
+static inline void
+intel_batchbuffer_require_space(struct brw_batch *batch, GLuint sz,
+                                enum brw_gpu_ring ring)
+{
+   /* If we're switching rings, implicitly flush the batch. */
+   if (unlikely(ring != batch->ring) && batch->ring != UNKNOWN_RING &&
+       batch->gen >= 6) {
+      brw_batch_flush(batch, NULL);
+   }
+
+#ifdef DEBUG
+   assert(sz < BATCH_SZ - BATCH_RESERVED);
+#endif
+   if (intel_batchbuffer_space(batch) < sz)
+      brw_batch_flush(batch, NULL);
+
+   enum brw_gpu_ring prev_ring = batch->ring;
+   /* The brw_batch_flush() calls above might have changed
+    * brw->batch.ring to UNKNOWN_RING, so we need to set it here at the end.
+    */
+   batch->ring = ring;
+
+   if (unlikely(prev_ring == UNKNOWN_RING && ring == RENDER_RING))
+      intel_batchbuffer_emit_render_ring_prelude(batch);
+}
+
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
index 9e06f4d..3c505a2 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
@@ -17,10 +17,6 @@ enum brw_gpu_ring;
 int intel_batchbuffer_init(struct brw_context *brw);
 void intel_batchbuffer_free(struct brw_context *brw);
 
-void intel_batchbuffer_save_state(struct brw_batch *batch);
-void intel_batchbuffer_reset_to_saved(struct brw_batch *batch);
-
-void intel_batchbuffer_emit_render_ring_prelude(struct brw_batch *batch);
 
 /* Unlike bmBufferData, this currently requires the buffer be mapped.
  * Consider it a convenience function wrapping multple
@@ -43,8 +39,6 @@ uint64_t intel_batchbuffer_reloc64(struct brw_context *brw,
                                    uint32_t write_domain,
                                    uint32_t delta);
 
-#define USED_BATCH(batch) ((uintptr_t)((batch)->map_next - (batch)->map))
-
 static inline uint32_t float_as_int(float f)
 {
    union {
@@ -61,14 +55,6 @@ static inline uint32_t float_as_int(float f)
  * be passed as structs rather than dwords, but that's a little bit of
  * work...
  */
-static inline unsigned
-intel_batchbuffer_space(struct brw_batch *batch)
-{
-   return (batch->state_batch_offset - batch->reserved_space)
-      - USED_BATCH(batch)*4;
-}
-
-
 static inline void
 intel_batchbuffer_emit_dword(struct brw_context *brw, GLuint dword)
 {
@@ -86,32 +72,6 @@ intel_batchbuffer_emit_float(struct brw_context *brw, float f)
 }
 
 static inline void
-intel_batchbuffer_require_space(struct brw_batch *batch, GLuint sz,
-                                enum brw_gpu_ring ring)
-{
-   /* If we're switching rings, implicitly flush the batch. */
-   if (unlikely(ring != batch->ring) && batch->ring != UNKNOWN_RING &&
-       batch->gen >= 6) {
-      brw_batch_flush(batch, NULL);
-   }
-
-#ifdef DEBUG
-   assert(sz < BATCH_SZ - BATCH_RESERVED);
-#endif
-   if (intel_batchbuffer_space(batch) < sz)
-      brw_batch_flush(batch, NULL);
-
-   enum brw_gpu_ring prev_ring = batch->ring;
-   /* The brw_batch_flush() calls above might have changed
-    * brw->batch.ring to UNKNOWN_RING, so we need to set it here at the end.
-    */
-   batch->ring = ring;
-
-   if (unlikely(prev_ring == UNKNOWN_RING && ring == RENDER_RING))
-      intel_batchbuffer_emit_render_ring_prelude(batch);
-}
-
-static inline void
 intel_batchbuffer_begin(struct brw_context *brw, int n, enum brw_gpu_ring ring)
 {
    intel_batchbuffer_require_space(&brw->batch, n * 4, ring);
-- 
2.5.0