[Mesa-dev] [PATCH 42/70] i965: Convert brw_emit_mi_flush() to use batch begin/end
Chris Wilson
chris at chris-wilson.co.uk
Fri Aug 7 13:13:46 PDT 2015
We have many flushes outside of the batch buffer critical sections that
need wrapping. Introduce a simple function to wrap the brw_emit_mi_flush()
with the begin/end.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
src/mesa/drivers/dri/i965/brw_clear.c | 4 ++--
src/mesa/drivers/dri/i965/brw_context.c | 2 +-
src/mesa/drivers/dri/i965/brw_context.h | 2 ++
src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 4 ++--
src/mesa/drivers/dri/i965/brw_meta_stencil_blit.c | 8 ++++----
src/mesa/drivers/dri/i965/brw_meta_updownsample.c | 4 ++--
src/mesa/drivers/dri/i965/brw_pipe_control.c | 9 +++++++++
src/mesa/drivers/dri/i965/gen6_sol.c | 3 +--
src/mesa/drivers/dri/i965/intel_blit.c | 2 +-
src/mesa/drivers/dri/i965/intel_buffer_objects.c | 4 ++--
src/mesa/drivers/dri/i965/intel_pixel_read.c | 2 +-
src/mesa/drivers/dri/i965/intel_syncobj.c | 2 +-
src/mesa/drivers/dri/i965/intel_tex_image.c | 2 +-
13 files changed, 29 insertions(+), 19 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c
index 571e692..3bf2d6d 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -183,7 +183,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
* must be issued before the rectangle primitive used for the depth
* buffer clear operation.
*/
- brw_emit_mi_flush(brw);
+ brw_mi_flush(brw, RENDER_RING);
if (fb->MaxNumLayers > 0) {
for (unsigned layer = 0; layer < depth_irb->layer_count; layer++) {
@@ -203,7 +203,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
* by a PIPE_CONTROL command with DEPTH_STALL bit set and Then
* followed by Depth FLUSH'
*/
- brw_emit_mi_flush(brw);
+ brw_mi_flush(brw, RENDER_RING);
}
/* Now, the HiZ buffer contains data that needs to be resolved to the depth
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 26041e6..2126d68 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -187,7 +187,7 @@ intel_update_state(struct gl_context * ctx, GLuint new_state)
intel_miptree_all_slices_resolve_depth(brw, tex_obj->mt);
intel_miptree_resolve_color(brw, tex_obj->mt);
if (brw_check_dirty(brw, tex_obj->mt->bo))
- brw_emit_mi_flush(brw);
+ brw_mi_flush(brw, RENDER_RING);
}
_mesa_lock_context_textures(ctx);
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index b9577c9..10b1e4e 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1981,6 +1981,8 @@ void brw_emit_depth_stall_flushes(struct brw_context *brw);
void gen7_emit_vs_workaround_flush(struct brw_context *brw);
void gen7_emit_cs_stall_flush(struct brw_context *brw);
+void brw_mi_flush(struct brw_context *brw, enum brw_gpu_ring ring);
+
bool brw_check_dirty(struct brw_context *ctx, brw_bo *bo);
#ifdef __cplusplus
diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
index ac2e08d..647bcf6 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
@@ -622,7 +622,7 @@ brw_meta_fast_clear(struct brw_context *brw, struct gl_framebuffer *fb,
* write-flush must be issued before sending any DRAW commands on that
* render target.
*/
- brw_emit_mi_flush(brw);
+ brw_mi_flush(brw, RENDER_RING);
/* If we had to fall back to plain clear for any buffers, clear those now
* by calling into meta.
@@ -676,7 +676,7 @@ brw_meta_resolve_color(struct brw_context *brw,
GLuint fbo, rbo;
struct rect rect;
- brw_emit_mi_flush(brw);
+ brw_mi_flush(brw, RENDER_RING);
_mesa_meta_begin(ctx, MESA_META_ALL);
diff --git a/src/mesa/drivers/dri/i965/brw_meta_stencil_blit.c b/src/mesa/drivers/dri/i965/brw_meta_stencil_blit.c
index 7f3577b..840d9d3 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_stencil_blit.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_stencil_blit.c
@@ -499,11 +499,11 @@ brw_meta_fbo_stencil_blit(struct brw_context *brw,
.mirror_x = mirror_x, .mirror_y = mirror_y };
adjust_mip_level(dst_mt, dst_irb->mt_level, dst_irb->mt_layer, &dims);
- brw_emit_mi_flush(brw);
+ brw_mi_flush(brw, RENDER_RING);
_mesa_meta_begin(ctx, MESA_META_ALL);
brw_meta_stencil_blit(brw,
dst_mt, dst_irb->mt_level, dst_irb->mt_layer, &dims);
- brw_emit_mi_flush(brw);
+ brw_mi_flush(brw, RENDER_RING);
}
void
@@ -523,7 +523,7 @@ brw_meta_stencil_updownsample(struct brw_context *brw,
if (dst->stencil_mt)
dst = dst->stencil_mt;
- brw_emit_mi_flush(brw);
+ brw_mi_flush(brw, RENDER_RING);
_mesa_meta_begin(ctx, MESA_META_ALL);
_mesa_GenFramebuffers(1, &fbo);
@@ -534,7 +534,7 @@ brw_meta_stencil_updownsample(struct brw_context *brw,
GL_RENDERBUFFER, rbo);
brw_meta_stencil_blit(brw, dst, 0, 0, &dims);
- brw_emit_mi_flush(brw);
+ brw_mi_flush(brw, RENDER_RING);
_mesa_DeleteRenderbuffers(1, &rbo);
_mesa_DeleteFramebuffers(1, &fbo);
diff --git a/src/mesa/drivers/dri/i965/brw_meta_updownsample.c b/src/mesa/drivers/dri/i965/brw_meta_updownsample.c
index 37a0968..c6dd822 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_updownsample.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_updownsample.c
@@ -115,7 +115,7 @@ brw_meta_updownsample(struct brw_context *brw,
blit_bit = GL_COLOR_BUFFER_BIT;
}
- brw_emit_mi_flush(brw);
+ brw_mi_flush(brw, RENDER_RING);
_mesa_meta_begin(ctx, MESA_META_ALL);
_mesa_GenFramebuffers(2, fbos);
@@ -146,5 +146,5 @@ brw_meta_updownsample(struct brw_context *brw,
_mesa_meta_end(ctx);
- brw_emit_mi_flush(brw);
+ brw_mi_flush(brw, RENDER_RING);
}
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index e513c15..67ff19b 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -330,6 +330,15 @@ brw_emit_mi_flush(struct brw_context *brw)
}
void
+brw_mi_flush(struct brw_context *brw, enum brw_gpu_ring ring)
+{
+ if (brw_batch_begin(&brw->batch, 60, ring) >= 0) {
+ brw_emit_mi_flush(brw);
+ brw_batch_end(&brw->batch);
+ }
+}
+
+void
brw_init_pipe_control(struct brw_context *brw,
const struct brw_device_info *devinfo)
{
diff --git a/src/mesa/drivers/dri/i965/gen6_sol.c b/src/mesa/drivers/dri/i965/gen6_sol.c
index 99db3d8..d75774c 100644
--- a/src/mesa/drivers/dri/i965/gen6_sol.c
+++ b/src/mesa/drivers/dri/i965/gen6_sol.c
@@ -292,6 +292,5 @@ brw_end_transform_feedback(struct gl_context *ctx,
* least the GS stage of the pipeline, and flush out the render cache. For
* simplicity, just do a full flush.
*/
- struct brw_context *brw = brw_context(ctx);
- brw_emit_mi_flush(brw);
+ brw_mi_flush(brw_context(ctx), RENDER_RING);
}
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index b6ad969..636e48a 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -560,7 +560,7 @@ intelEmitCopyBlit(struct brw_context *brw,
*
* FIXME: Figure out a way to avoid flushing when not required.
*/
- brw_emit_mi_flush(brw);
+ brw_mi_flush(brw, BLT_RING);
assert(cpp <= 16);
BR13 = br13_for_cpp(cpp);
diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
index fcbec9a..0cd997e 100644
--- a/src/mesa/drivers/dri/i965/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
@@ -559,7 +559,7 @@ brw_unmap_buffer(struct gl_context *ctx,
* flush. Once again, we wish for a domain tracker in libdrm to cover
* usage inside of a batchbuffer.
*/
- brw_emit_mi_flush(brw);
+ brw_mi_flush(brw, BLT_RING);
brw_bo_put(intel_obj->range_map_bo[index]);
intel_obj->range_map_bo[index] = NULL;
@@ -631,7 +631,7 @@ brw_copy_buffer_subdata(struct gl_context *ctx,
* flush. Once again, we wish for a domain tracker in libdrm to cover
* usage inside of a batchbuffer.
*/
- brw_emit_mi_flush(brw);
+ brw_mi_flush(brw, BLT_RING);
}
void
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read.c b/src/mesa/drivers/dri/i965/intel_pixel_read.c
index ce71a75..c0cf5d6 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_read.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_read.c
@@ -244,7 +244,7 @@ intelReadPixels(struct gl_context * ctx,
* rendered to via a PBO at any point, so it seems better to just
* flush here unconditionally.
*/
- brw_emit_mi_flush(brw);
+ brw_mi_flush(brw, BLT_RING);
return;
}
diff --git a/src/mesa/drivers/dri/i965/intel_syncobj.c b/src/mesa/drivers/dri/i965/intel_syncobj.c
index 2faf953..00b9e73 100644
--- a/src/mesa/drivers/dri/i965/intel_syncobj.c
+++ b/src/mesa/drivers/dri/i965/intel_syncobj.c
@@ -67,7 +67,7 @@ brw_fence_insert(struct brw_context *brw, struct brw_fence *fence)
assert(!fence->batch_bo);
assert(!fence->signalled);
- brw_emit_mi_flush(brw);
+ brw_mi_flush(brw, RENDER_RING);
fence->batch_bo = brw_bo_get(brw->batch.bo);
brw_batch_flush(&brw->batch, PERF_DEBUG(brw, "SyncFence"));
}
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 0ce63ef..123b05e 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -489,7 +489,7 @@ intel_get_tex_sub_image(struct gl_context *ctx,
* See the related comment in intelReadPixels() for a more detailed
* explanation.
*/
- brw_emit_mi_flush(brw);
+ brw_mi_flush(brw, BLT_RING);
return;
}
--
2.5.0
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