[Mesa-dev] [PATCH] i965: Move control flush into pipelined conditional render

Chris Wilson chris at chris-wilson.co.uk
Fri Aug 21 09:14:05 PDT 2015

On Fri, Aug 21, 2015 at 04:14:25PM +0100, Chris Wilson wrote:
> The nv_conditional_render piglits were sporadically failing. Moving
> the control flush from the write and placing it just before the read
> was sufficient to make the piglits pass a 1000/1000 times. The bspec
> says that the flush enable bit "waits until all previous writes of
> immediate data from post sync circles are complete before executing the
> next commend" - the operative word being previous!
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90691

Chris Wilson, Intel Open Source Technology Centre

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