[Mesa-dev] [PATCH] r600g: Fix handling of TGSI_OPCODE_ARR with SB

[Vadim Girlin]

On 08/13/15 21:30, Glenn Kennard wrote:
> FLT_TO_INT goes in the vector pipes on evergreen/NI,
> not the trans unit as on earlier chips.

FWIW, AFAIK it works in trans as well, just uses different rounding mode.

According to the description in the EG ISA doc: "Channels 0-3 use
the 32-bit round mode state; channel 4 uses truncation.".

So vector slots use default rounding mode, trans slot always uses trunc.

That is, I have no objections against that change, I think it makes 
sense to limit it to expected behavior, I hoped to control it somewhere 
later, but didn't ever get close to it.

So just FYI.


>
> Signed-off-by: Glenn Kennard <glenn.kennard at gmail.com>
> ---
> Fixes issue found on nine: https://github.com/iXit/Mesa-3D/issues/119
>
>   src/gallium/drivers/r600/r600_isa.h | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/r600/r600_isa.h b/src/gallium/drivers/r600/r600_isa.h
> index 381f06d..fdbe1c0 100644
> --- a/src/gallium/drivers/r600/r600_isa.h
> +++ b/src/gallium/drivers/r600/r600_isa.h
> @@ -262,7 +262,7 @@ static const struct alu_op_info alu_op_table[] = {
>   		{"PRED_SETNE_PUSH_INT",       2, { 0x4D, 0x4D },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED_PUSH | AF_CC_NE | AF_INT_CMP },
>   		{"PRED_SETLT_PUSH_INT",       2, { 0x4E, 0x4E },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED_PUSH | AF_CC_LT | AF_INT_CMP },
>   		{"PRED_SETLE_PUSH_INT",       2, { 0x4F, 0x4F },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED_PUSH | AF_CC_LE | AF_INT_CMP },
> -		{"FLT_TO_INT",                1, { 0x6B, 0x50 },{   AF_S,  AF_S, AF_VS, AF_VS},  AF_INT_DST | AF_CVT },
> +		{"FLT_TO_INT",                1, { 0x6B, 0x50 },{   AF_S,  AF_S,  AF_V,  AF_V},  AF_INT_DST | AF_CVT },
>   		{"BFREV_INT",                 1, {   -1, 0x51 },{      0,     0, AF_VS, AF_VS},  AF_INT_DST },
>   		{"ADDC_UINT",                 2, {   -1, 0x52 },{      0,     0, AF_VS, AF_VS},  AF_UINT_DST },
>   		{"SUBB_UINT",                 2, {   -1, 0x53 },{      0,     0, AF_VS, AF_VS},  AF_UINT_DST },
>