[Mesa-dev] [PATCH] r600g: add proper support for VGT_FLUSH

[Dave Airlie]

From: Dave Airlie <airlied at redhat.com>

The geom shader rings require a VGT FLUSH, but up until now
it was just hacked into the function, add proper support for it.

Signed-off-by: Dave Airlie <airlied at redhat.com>
---
 src/gallium/drivers/r600/evergreen_state.c | 9 +--------
 src/gallium/drivers/r600/r600_hw_context.c | 5 +++++
 src/gallium/drivers/r600/r600_pipe.h       | 3 ++-
 3 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 6a91d47..a44646a 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -2173,10 +2173,6 @@ static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom
 	struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
 	struct r600_resource *rbuffer;
 
-	r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
-	radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
-	radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
-
 	if (state->enable) {
 		rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
 		r600_write_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
@@ -2201,10 +2197,7 @@ static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom
 		r600_write_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
 		r600_write_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
 	}
-
-	r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
-	radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
-	radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
+	rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_VGT_FLUSH;
 }
 
 void cayman_init_common_regs(struct r600_command_buffer *cb,
diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c
index 6445151..5cef9dd 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -128,6 +128,11 @@ void r600_flush_emit(struct r600_context *rctx)
 		cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
 	}
 
+	if (rctx->b.flags & R600_CONTEXT_VGT_FLUSH) {
+		cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
+		cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_VGT_FLUSH) | EVENT_INDEX(0);
+	}
+
 	if (rctx->b.chip_class >= R700 &&
 	    (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV_CB_META)) {
 		cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index 3247aba..b77d136 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -54,9 +54,10 @@
 #define R600_CONTEXT_PS_PARTIAL_FLUSH		(R600_CONTEXT_PRIVATE_FLAG << 8)
 #define R600_CONTEXT_WAIT_3D_IDLE		(R600_CONTEXT_PRIVATE_FLAG << 9)
 #define R600_CONTEXT_WAIT_CP_DMA_IDLE		(R600_CONTEXT_PRIVATE_FLAG << 10)
+#define R600_CONTEXT_VGT_FLUSH		(R600_CONTEXT_PRIVATE_FLAG << 11)
 
 /* the number of CS dwords for flushing and drawing */
-#define R600_MAX_FLUSH_CS_DWORDS	16
+#define R600_MAX_FLUSH_CS_DWORDS	18
 #define R600_MAX_DRAW_CS_DWORDS		47
 #define R600_TRACE_CS_DWORDS		7
 
-- 
2.4.3