[Mesa-dev] [PATCH] i965: Add defines for gather push constants

Ilia Mirkin imirkin at alum.mit.edu
Mon Dec 7 06:45:26 PST 2015


On Mon, Dec 7, 2015 at 7:39 AM, Abdiel Janulgue
<abdiel.janulgue at linux.intel.com> wrote:
> v2 (Francisco Jerez):
>    - Rename HSW_GATHER_CONSTANTS_RESERVED to HSW_GATHER_POOL_ALLOC_MUST_BE_ONE.
>    - Rename BRW_GATHER_* prefix to HSW_GATHER_CONSTANTS_*.
>
> Signed-off-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
> ---
>  src/mesa/drivers/dri/i965/brw_defines.h | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
> index a511d5c..f997cf9 100644
> --- a/src/mesa/drivers/dri/i965/brw_defines.h
> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> @@ -2565,6 +2565,25 @@ enum brw_wm_barycentric_interp_mode {
>  #define _3DSTATE_CONSTANT_HS                  0x7819 /* GEN7+ */
>  #define _3DSTATE_CONSTANT_DS                  0x781A /* GEN7+ */
>
> +/* Resource streamer gather constants */
> +#define HSW_GATHER_POOL_ALLOC_MUST_BE_ONE     (3 << 4) /* GEN7.5 only */
> +#define _3DSTATE_GATHER_POOL_ALLOC            0x791A /* GEN7.5+ */
> +#define _3DSTATE_GATHER_CONSTANT_VS           0x7834
> +#define _3DSTATE_GATHER_CONSTANT_GS           0x7835
> +#define _3DSTATE_GATHER_CONSTANT_HS           0x7836
> +#define _3DSTATE_GATHER_CONSTANT_DS           0x7837
> +#define _3DSTATE_GATHER_CONSTANT_PS           0x7838
> +
> +#define HSW_GATHER_CONSTANTS_ENABLE           (1 << 11) /* GEN7.5+ */
> +#define HSW_GATHER_CONSTANTS_BUFFER_VALID_SHIFT         16
> +#define HSW_GATHER_CONSTANTS_BUFFER_VALID_MASK          INTEL_MASK(31, 16)
> +#define HSW_GATHER_CONSTANTS_BINDING_TABLE_BLOCK_SHIFT  12
> +#define HSW_GATHER_CONSTANTS_BINDING_TABLE_BLOCK_MASK   INTEL_MASK(15, 12)
> +#define HSW_GATHER_CONSTANTS_CONST_BUFFER_OFFSET_SHIFT  8
> +#define HSW_GATHER_CONSTANTS_CONST_BUFFER_OFFSET_MASK   INTEL_MASK(15, 8)

I mentioned this on IRC, but shouldn't this one have been
INTEL_MASK(11, 8)? Seems unlikely that there are overlapping
bitfields...

  -ilia

> +#define HSW_GATHER_CONSTANTS_CHANNEL_MASK_SHIFT         4
> +#define HSW_GATHER_CONSTANTS_CHANNEL_MASK_MASK          INTEL_MASK(7, 4)
> +
>  #define _3DSTATE_STREAMOUT                    0x781e /* GEN7+ */
>  /* DW1 */
>  # define SO_FUNCTION_ENABLE                            (1 << 31)
> --
> 1.9.1
>
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