[Mesa-dev] [PATCH] i965: Only apply CS stall workaround pre-SKL

[Kenneth Graunke]

On Thursday, December 17, 2015 01:21:26 PM Ben Widawsky wrote:
> As per the docs.
> 
> Cc: Kenneth Graunke <kenneth at whitecape.org>
> Signed-off-by: Ben Widawsky <benjamin.widawsky at intel.com>
> ---
>  src/mesa/drivers/dri/i965/brw_pipe_control.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
> index ae3d818..6c636d2 100644
> --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
> +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
> @@ -97,7 +97,8 @@ void
>  brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags)
>  {
>     if (brw->gen >= 8) {
> -      gen8_add_cs_stall_workaround_bits(&flags);
> +      if (brw->gen == 8)
> +         gen8_add_cs_stall_workaround_bits(&flags);
>  
>        BEGIN_BATCH(6);
>        OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
> @@ -141,7 +142,8 @@ brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
>                              uint32_t imm_lower, uint32_t imm_upper)
>  {
>     if (brw->gen >= 8) {
> -      gen8_add_cs_stall_workaround_bits(&flags);
> +      if (brw->gen == 8)
> +         gen8_add_cs_stall_workaround_bits(&flags);
>  
>        BEGIN_BATCH(6);
>        OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
> 

"No restrictions."  Hard to believe, but that's what it says :)

Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
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