[Mesa-dev] New stable-branch 11.0 candidate pushed

Emil Velikov emil.l.velikov at gmail.com
Fri Dec 18 05:19:16 PST 2015


Hello list,

The candidate for the Mesa 11.0.8 is now available. Currently we have:
 - 54 queued
 - 17 nominated (outstanding)
 - and 1 rejected/obsolete patches

Current queue covers a significant amount of fixes - from radeonsi
(Fiji, Hyper-Z), r600 (geom. shaders), nouveau (ir), freedreno (piglits),
i965 (UBOs) and a few patches for "GRID Autosport" (i965 and glsl).

Last but not least - a few more BSD related build fixes are included :-)


Take a look at section "Mesa stable queue" for more information.


Dave, Marek,

A few commits in the nominated list require backports. Please forward
them to mesa-stable mailing list.


Testing
-------
The following results are against piglit 4b6848c131c.


Changes - classic i965(snb)
---------------------------
None.


Changes - swrast classic
------------------------
None.


Changes - gallium softpipe
--------------------------
None.


Changes - gallium llvmpipe (LLVM 3.7)
-------------------------------------
None.


Testing reports/general approval
--------------------------------
Any testing reports (or general approval of the state of the branch)
will be greatly appreciated.


Trivial merge conflicts
-----------------------
commit 1ee592b09554983c46405ad8e6396921ae52935d
Author: Ilia Mirkin <imirkin at alum.mit.edu>

    freedreno/a4xx: point regid to "red" even for alpha-only rb formats

    (cherry picked from commit ff9450ecd1f7635f8917e3177f0ef18eb8f9f49b)


commit 3965a21e9506e48dd0927efb2df26963e84bcdc1
Author: Tom Stellard <thomas.stellard at amd.com>

    radeonsi: Rename si_shader::ls_rsrc{1,2} to si_shader::rsrc{1,2}

    (cherry picked from commit 95e051091676584fd7bfba9d0316c3747bf17f35)


commit b9dbe209106f83880f6432b95f65b76eb20b5f00
Author: Tom Stellard <thomas.stellard at amd.com>

    radeonsi/compute: Use the compiler's COMPUTE_PGM_RSRC* register values

    (cherry picked from commit 89851a296536b89364fe6104d13330975788f960)


commit 147c3fbdb3f779f5172304e3be10cc27e0e67be7
Author: Jason Ekstrand <jason.ekstrand at intel.com>

    i965/fs: Use a stride of 1 and byte offsets for UBOs

    (cherry picked from commit 13ad8d03f201a4d09bf7ab9078b00807d61dfada)


commit 147c3fbdb3f779f5172304e3be10cc27e0e67be7
Author: Jason Ekstrand <jason.ekstrand at intel.com>

    i965/vec4: Use a stride of 1 and byte offsets for UBOs

    (cherry picked from commit 05bdc21f84edc200a0b0a695b79d12f25cc00645)


commit 683d65dae3e673ee95d544008874edf1255e87cf
Author: Jason Ekstrand <jason.ekstrand at intel.com>

    i965/state: Get rid of dword_pitch arguments to buffer functions

    (cherry picked from commit abb569ca18db159ae3e4c4b51d01e5a8b3215e04)


commit 4acb394f459b58725a2059a911b6236703c44eb2
Author: Jason Ekstrand <jason.ekstrand at intel.com>

    i965/nir: Remove unused indirect handling

    (cherry picked from commit 22c273de2b97743587310f7bbf66767191bde866)


commit e1a5b7a86361b5e2c10d22a65aab236d319937c0
Author: Marek Olšák <marek.olsak at amd.com>

    gallium/radeon: fix Hyper-Z hangs by programming PA_SC_MODE_CNTL_1 correctly

    (cherry picked from commit d3c08309abd17b6e0d466b677af57e3cc74b0e00)


commit a82422f4a463e435ed8a9d356acbe0524d6fe3d4
Author: Jonathan Gray <jsg at jsg.id.au>

    configure.ac: use pkg-config for libelf

    (cherry picked from commit 7f585a6a98d0553ec0ba48e18b1d9bac1256881a)


The plan is to have 11.0.8 this Sunday (20th of December), some
time after 13:00 GMT.

If you have any questions or comments that you would like to share
before the release, please go ahead.


Cheers,
Emil


Mesa stable queue
-----------------

Nominated (17)
==============

Boyan Ding (1):
      i915: Add XRGB8888 format to intel_screen_make_configs

Boyuan Zhang (1):
      radeon/uvd: uv pitch separation for stoney

Brian Paul (1):
      configure: don't try to build gallium DRI drivers if --disable-dri is set

Dave Airlie (2):
    r600g: fix outputing to non-0 buffers for stream 0.
    radeonsi: handle loading doubles as geometry shader inputs.                                                                                                                                                                   

* Dave can you send backports for these. Alternatively I'm inclined on drop
them, as they diverge from 11.0 a fair bit.


Dawid Gan (1):
      i965: handle stencil_bits parameter for MESA_FORMAT_B8G8R8X8_UNORM format.

Emil Velikov (2):
      i965: store reference to the context within struct brw_fence
      egl/dri2: expose srgb configs when KHR_gl_colorspace is available

Ilia Mirkin (1):
      ttn: add TEX2 support

* Just noticed this if fell off the radar due to me "rejecting it". Will pick it
up before the release.


Jean-Sébastien Pédron (1):
      ralloc: Use __attribute__((destructor)) instead of atexit(3)

Kenneth Graunke (1):
      ralloc: Fix ralloc_adopt() to the old context's last child's parent.

Marek Olšák (2):
    tgsi/scan: add flag colors_written
    r600g: write all MRTs only if there is exactly one output (fixes a hang)
    
* Marek can you send backport the latter. Alternatively I'm inclined on drop
them, as it diverges from 11.0 a fair bit.


Tom Stellard (4):
      clover: Call clBuildProgram() notification function when build completes v2
      gallium/drivers: Add threadsafe wrappers for pipe_context v2
      clover: Use threadsafe wrappers for pipe_context v2
      clover: Properly initialize LLVM targets when linking with component libs



Queued (54)
===========

Dave Airlie (9):
      r600: do SQ flush ES ring rolling workaround
      r600: SMX returns CONTEXT_DONE early workaround
      r600/shader: split address get out to a function.
      r600/shader: add utility functions to do single slot arithmatic
      r600g: fix geom shader input indirect indexing.
      r600: handle geometry dynamic input array index
      radeonsi: handle doubles in lds load path.
      mesa/varray: set double arrays to non-normalised.
      mesa/shader: return correct attribute location for double matrix arrays

Emil Velikov (2):
      docs: add sha256 checksums for 11.0.7
      cherry-ignore: don't pick a specific i965 formats patch

Francisco Jerez (1):
      i965: Resolve color and flush for all active shader images in intel_update_state().

Ian Romanick (1):
      meta/generate_mipmap: Work-around GLES 1.x problem with GL_DRAW_FRAMEBUFFER

Ilia Mirkin (16):
      freedreno/a4xx: support lod_bias
      freedreno/a4xx: fix 5_5_5_1 texture sampler format
      freedreno/a4xx: point regid to "red" even for alpha-only rb formats
      nvc0/ir: fold postfactor into immediate
      nv50/ir: deal with loops with no breaks
      nv50/ir: the mad source might not have a defining instruction
      nv50/ir: fix instruction permutation logic
      nv50/ir: don't forget to mark flagsDef on cvt in txb lowering
      nv50/ir: fix DCE to not generate 96-bit loads
      nv50/ir: avoid looking at uninitialized srcMods entries
      gk110/ir: fix imul hi emission with limm arg
      gk104/ir: sampler doesn't matter for txf
      gk110/ir: fix imad sat/hi flag emission for immediate args
      nv50/ir: fix cutoff for using r63 vs r127 when replacing zero
      nv50/ir: can't have predication and immediates
      glsl: assign varying locations to tess shaders when doing SSO

Jason Ekstrand (5):
      i965/vec4: Use byte offsets for UBO pulls on Sandy Bridge
      i965/fs: Use a stride of 1 and byte offsets for UBOs
      i965/vec4: Use a stride of 1 and byte offsets for UBOs
      i965/state: Get rid of dword_pitch arguments to buffer functions
      i965/nir: Remove unused indirect handling

Jonathan Gray (2):
      configure.ac: use pkg-config for libelf
      configure: check for python2.7 for PYTHON2

Kenneth Graunke (2):
      i965: Fix fragment shader struct inputs.
      i965: Fix scalar vertex shader struct outputs.

Marek Olšák (6):
      radeonsi: fix occlusion queries on Fiji
      radeonsi: fix a hang due to uninitialized border color registers
      radeonsi: fix Fiji for LLVM <= 3.7
      radeonsi: don't call of u_prims_for_vertices for patches and rectangles
      radeonsi: apply the streamout workaround to Fiji as well
      gallium/radeon: fix Hyper-Z hangs by programming PA_SC_MODE_CNTL_1 correctly

Matt Turner (1):
      glsl: Allow binding of image variables with 420pack.

Neil Roberts (2):
      i965: Add MESA_FORMAT_B8G8R8X8_SRGB to brw_format_for_mesa_format
      i965: Add B8G8R8X8_SRGB to the alpha format override

Oded Gabbay (1):
      configura.ac: fix test for SSE4.1 assembler support

Patrick Rudolph (2):
      nv50,nvc0: fix use-after-free when vertex buffers are unbound
      gallium/util: return correct number of bound vertex buffers

Samuel Pitoiset (1):
      nvc0: free memory allocated by the prog which reads MP perf counters

Tapani Pälli (1):
      i965: use _Shader to get fragment program when updating surface state

Tom Stellard (2):
      radeonsi: Rename si_shader::ls_rsrc{1,2} to si_shader::rsrc{1,2}
      radeonsi/compute: Use the compiler's COMPUTE_PGM_RSRC* register values


Superseded (1)
==============

Jonathan Gray (1):
      configure.ac: fix test for SSE4.1 assembler support



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