[Mesa-dev] [PATCH] nvc0: add hardware ETC2 and ASTC support where possible
Ilia Mirkin
imirkin at alum.mit.edu
Mon Dec 21 11:53:00 PST 2015
On Sat, Dec 19, 2015 at 6:06 PM, Ilia Mirkin <imirkin at alum.mit.edu> wrote:
> On Sat, Dec 19, 2015 at 1:53 PM, Ilia Mirkin <imirkin at alum.mit.edu> wrote:
>> These are supported on GK20A and GM107.
>>
>> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
>> ---
>>
>> Was a bit torn on where to place the enums... we're about to gut all
>> the xml definitions so this seemed appropriate for now.
>>
>> Tested on GK20A only.
>>
>> src/gallium/drivers/nouveau/nv50/nv50_formats.c | 64 +++++++++++++++++++++++++
>> src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 10 ++++
>> src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 4 +-
>> 3 files changed, 77 insertions(+), 1 deletion(-)
>>
>> diff --git a/src/gallium/drivers/nouveau/nv50/nv50_formats.c b/src/gallium/drivers/nouveau/nv50/nv50_formats.c
>> index 49a93bf..971fc64 100644
>> --- a/src/gallium/drivers/nouveau/nv50/nv50_formats.c
>> +++ b/src/gallium/drivers/nouveau/nv50/nv50_formats.c
>> @@ -84,6 +84,29 @@
>> #define NV50_TIC_0_FMT_BPTC_FLOAT NVC0_TIC_0_FMT_BPTC_FLOAT
>> #define NV50_TIC_0_FMT_BPTC_UFLOAT NVC0_TIC_0_FMT_BPTC_UFLOAT
>>
>> +/* GK20A and GM107+ formats */
>> +#define NV50_TIC_0_FMT_ETC2_RGB 0x06
>> +#define NV50_TIC_0_FMT_ETC2_RGBA1 0x0a
>> +#define NV50_TIC_0_FMT_ETC2_RGBA 0x0b
>> +#define NV50_TIC_0_FMT_ETC2_R11 0x19
>> +#define NV50_TIC_0_FMT_ETC2_RG11 0x1a
>> +
>> +/* On GK20A, the high bit goes elsewhere */
>> +#define NV50_TIC_0_FMT_ASTC_2D_4X4 0x40
>> +#define NV50_TIC_0_FMT_ASTC_2D_5X4 0x50
>> +#define NV50_TIC_0_FMT_ASTC_2D_5X5 0x41
>> +#define NV50_TIC_0_FMT_ASTC_2D_6X5 0x51
>> +#define NV50_TIC_0_FMT_ASTC_2D_6X6 0x42
>> +#define NV50_TIC_0_FMT_ASTC_2D_8X5 0x55
>> +#define NV50_TIC_0_FMT_ASTC_2D_8X6 0x52
>> +#define NV50_TIC_0_FMT_ASTC_2D_8X8 0x44
>> +#define NV50_TIC_0_FMT_ASTC_2D_10X5 0x56
>> +#define NV50_TIC_0_FMT_ASTC_2D_10X6 0x57
>> +#define NV50_TIC_0_FMT_ASTC_2D_10X8 0x53
>> +#define NV50_TIC_0_FMT_ASTC_2D_10X10 0x45
>> +#define NV50_TIC_0_FMT_ASTC_2D_12X10 0x54
>> +#define NV50_TIC_0_FMT_ASTC_2D_12X12 0x46
>> +
>> #if NOUVEAU_DRIVER == 0xc0
>> # define NVXX_3D_VAF_SIZE(s) NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_##s
>> # define NVXX_3D_VAF_TYPE(t) NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_##t
>> @@ -296,6 +319,47 @@ const struct nv50_format nv50_format_table[PIPE_FORMAT_COUNT] =
>> F3B(BPTC_RGB_FLOAT, NONE, C0, C1, C2, xx, FLOAT, BPTC_FLOAT, t),
>> F3B(BPTC_RGB_UFLOAT, NONE, C0, C1, C2, xx, FLOAT, BPTC_UFLOAT, t),
>>
>> + F3B(ETC2_RGB8, NONE, C0, C1, C2, xx, UNORM, ETC2_RGB, t),
>> + F3B(ETC2_SRGB8, NONE, C0, C1, C2, xx, UNORM, ETC2_RGB, t),
>> + C4B(ETC2_RGB8A1, NONE, C0, C1, C2, C3, UNORM, ETC2_RGBA1, t),
>> + C4B(ETC2_SRGB8A1, NONE, C0, C1, C2, C3, UNORM, ETC2_RGBA1, t),
>> + C4B(ETC2_RGBA8, NONE, C0, C1, C2, C3, UNORM, ETC2_RGBA, t),
>> + C4B(ETC2_SRGBA8, NONE, C0, C1, C2, C3, UNORM, ETC2_RGBA, t),
>> + F1B(ETC2_R11_UNORM, NONE, C0, xx, xx, xx, UNORM, ETC2_R11, t),
>> + F1B(ETC2_R11_SNORM, NONE, C0, xx, xx, xx, SNORM, ETC2_R11, t),
>> + F2B(ETC2_RG11_UNORM, NONE, C0, C1, xx, xx, UNORM, ETC2_RG11, t),
>> + F2B(ETC2_RG11_SNORM, NONE, C0, C1, xx, xx, SNORM, ETC2_RG11, t),
>> +
>> + C4B(ASTC_4x4, NONE, C0, C1, C2, C3, UNORM, ASTC_2D_4X4, t),
>> + C4B(ASTC_5x4, NONE, C0, C1, C2, C3, UNORM, ASTC_2D_5X4, t),
>> + C4B(ASTC_5x5, NONE, C0, C1, C2, C3, UNORM, ASTC_2D_5X5, t),
>> + C4B(ASTC_6x5, NONE, C0, C1, C2, C3, UNORM, ASTC_2D_6X5, t),
>> + C4B(ASTC_6x6, NONE, C0, C1, C2, C3, UNORM, ASTC_2D_6X6, t),
>> + C4B(ASTC_8x5, NONE, C0, C1, C2, C3, UNORM, ASTC_2D_8X5, t),
>> + C4B(ASTC_8x6, NONE, C0, C1, C2, C3, UNORM, ASTC_2D_8X6, t),
>> + C4B(ASTC_8x8, NONE, C0, C1, C2, C3, UNORM, ASTC_2D_8X8, t),
>> + C4B(ASTC_10x5, NONE, C0, C1, C2, C3, UNORM, ASTC_2D_10X5, t),
>> + C4B(ASTC_10x6, NONE, C0, C1, C2, C3, UNORM, ASTC_2D_10X6, t),
>> + C4B(ASTC_10x8, NONE, C0, C1, C2, C3, UNORM, ASTC_2D_10X8, t),
>> + C4B(ASTC_10x10, NONE, C0, C1, C2, C3, UNORM, ASTC_2D_10X10, t),
>> + C4B(ASTC_12x10, NONE, C0, C1, C2, C3, UNORM, ASTC_2D_12X10, t),
>> + C4B(ASTC_12x12, NONE, C0, C1, C2, C3, UNORM, ASTC_2D_12X12, t),
>> +
>> + C4B(ASTC_4x4_SRGB, NONE, C0, C1, C2, C3, UNORM, ASTC_2D_4X4, t),
>> + C4B(ASTC_5x4_SRGB, NONE, C0, C1, C2, C3, UNORM, ASTC_2D_5X4, t),
>> + C4B(ASTC_5x5_SRGB, NONE, C0, C1, C2, C3, UNORM, ASTC_2D_5X5, t),
>> + C4B(ASTC_6x5_SRGB, NONE, C0, C1, C2, C3, UNORM, ASTC_2D_6X5, t),
>> + C4B(ASTC_6x6_SRGB, NONE, C0, C1, C2, C3, UNORM, ASTC_2D_6X6, t),
>> + C4B(ASTC_8x5_SRGB, NONE, C0, C1, C2, C3, UNORM, ASTC_2D_8X5, t),
>> + C4B(ASTC_8x6_SRGB, NONE, C0, C1, C2, C3, UNORM, ASTC_2D_8X6, t),
>> + C4B(ASTC_8x8_SRGB, NONE, C0, C1, C2, C3, UNORM, ASTC_2D_8X8, t),
>> + C4B(ASTC_10x5_SRGB, NONE, C0, C1, C2, C3, UNORM, ASTC_2D_10X5, t),
>> + C4B(ASTC_10x6_SRGB, NONE, C0, C1, C2, C3, UNORM, ASTC_2D_10X6, t),
>> + C4B(ASTC_10x8_SRGB, NONE, C0, C1, C2, C3, UNORM, ASTC_2D_10X8, t),
>> + C4B(ASTC_10x10_SRGB, NONE, C0, C1, C2, C3, UNORM, ASTC_2D_10X10, t),
>> + C4B(ASTC_12x10_SRGB, NONE, C0, C1, C2, C3, UNORM, ASTC_2D_12X10, t),
>> + C4B(ASTC_12x12_SRGB, NONE, C0, C1, C2, C3, UNORM, ASTC_2D_12X12, t),
>> +
>> C4A(R32G32B32A32_FLOAT, RGBA32_FLOAT, C0, C1, C2, C3, FLOAT, 32_32_32_32,
>> IBV, 0),
>> C4A(R32G32B32A32_UNORM, NONE, C0, C1, C2, C3, UNORM, 32_32_32_32, TV, 0),
>> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
>> index 4757fe2..1c88580 100644
>> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
>> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
>> @@ -43,6 +43,7 @@ nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
>> unsigned sample_count,
>> unsigned bindings)
>> {
>> + const struct util_format_description *desc = util_format_description(format);
>> if (sample_count > 8)
>> return false;
>> if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
>> @@ -55,6 +56,15 @@ nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
>> if (util_format_get_blocksizebits(format) == 3 * 32)
>> return false;
>>
>> + /* Restrict ETC2 and ASTC formats here. These are only supported on GM107+
>> + * and GK20A.
>> + */
>> + if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
>> + desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
>> + nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
>> + nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
>> + return false;
>> +
>> /* transfers & shared are always supported */
>> bindings &= ~(PIPE_BIND_TRANSFER_READ |
>> PIPE_BIND_TRANSFER_WRITE |
>> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
>> index 74090ce..bc648fe 100644
>> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
>> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
>> @@ -102,7 +102,9 @@ nvc0_create_texture_view(struct pipe_context *pipe,
>>
>> desc = util_format_description(view->pipe.format);
>>
>> - tic[0] = nvc0_format_table[view->pipe.format].tic;
>> + tic[0] = nvc0_format_table[view->pipe.format].tic & 0x3f;
>
> Naturally this needs to be ~0x40. Oops. Fixed locally.
Withdrawn. This is just plain wrong -- that bit is part of the
swizzle. I need a better way of moving the high bit of the format into
position.
>
>> + if (nvc0_format_table[view->pipe.format].tic & 0x40)
>> + tic[0] |= 1U << 31;
>>
>> tex_int = util_format_is_pure_integer(view->pipe.format);
>>
>> --
>> 2.4.10
>>
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