[Mesa-dev] [PATCH] r600: fix constant buffer size programming

[Nicolai Hähnle]

On 21.12.2015 21:12, Grazvydas Ignotas wrote:
> When buffer size is less than 16, zero ends up being programmed as
> size, which prevents the hardware from fetching the correct values.
> Fix it by combining shift and align so that the value is always
> rounded up.
>
> Cc: "11.1 11.0 10.6" <mesa-stable at lists.freedesktop.org>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92229
> Signed-off-by: Grazvydas Ignotas <notasas at gmail.com>
> ---
>   Only tested on Juniper, but I guess others will need this too.

Nice catch.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

Do you have commit access?

>   src/gallium/drivers/r600/evergreen_state.c | 2 +-
>   src/gallium/drivers/r600/r600_state.c      | 2 +-
>   2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
> index 1443bc0..1aee7dd 100644
> --- a/src/gallium/drivers/r600/evergreen_state.c
> +++ b/src/gallium/drivers/r600/evergreen_state.c
> @@ -1956,7 +1956,7 @@ static void evergreen_emit_constant_buffers(struct r600_context *rctx,
>
>   		if (!gs_ring_buffer) {
>   			radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
> -						    ALIGN_DIVUP(cb->buffer_size >> 4, 16), pkt_flags);
> +						    ALIGN_DIVUP(cb->buffer_size, 256), pkt_flags);
>   			radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
>   						    pkt_flags);
>   		}
> diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
> index e7ffe0d..43b8074 100644
> --- a/src/gallium/drivers/r600/r600_state.c
> +++ b/src/gallium/drivers/r600/r600_state.c
> @@ -1768,7 +1768,7 @@ static void r600_emit_constant_buffers(struct r600_context *rctx,
>
>   		if (!gs_ring_buffer) {
>   			radeon_set_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
> -					       ALIGN_DIVUP(cb->buffer_size >> 4, 16));
> +					       ALIGN_DIVUP(cb->buffer_size, 256));
>   			radeon_set_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
>   		}
>
>