[Mesa-dev] [PATCH] i965: Don't tile 1D miptrees.

Neil Roberts neil at linux.intel.com
Mon Feb 9 09:47:38 PST 2015


Looks good to me.

Reviewed-by: Neil Roberts <neil at linux.intel.com>

- Neil

Francisco Jerez <currojerez at riseup.net> writes:

> It doesn't really improve locality of texture fetches, quite the
> opposite it's a waste of memory bandwidth and space due to tile
> alignment.
>
> v2: Check mt->logical_height0 instead of mt->target (Ken).  Add short
>     comment explaining why they shouldn't be tiled.
> ---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 64752dd..0e3888f 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -488,6 +488,13 @@ intel_miptree_choose_tiling(struct brw_context *brw,
>         base_format == GL_DEPTH_STENCIL_EXT)
>        return I915_TILING_Y;
>  
> +   /* 1D textures (and 1D array textures) don't get any benefit from tiling,
> +    * in fact it leads to a less efficient use of memory space and bandwidth
> +    * due to tile alignment.
> +    */
> +   if (mt->logical_height0 == 1)
> +      return I915_TILING_NONE;
> +
>     int minimum_pitch = mt->total_width * mt->cpp;
>  
>     /* If the width is much smaller than a tile, don't bother tiling. */
> -- 
> 2.1.3
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