[Mesa-dev] [PATCH 3/3] i965/fs/nir: Optimize integer multiply by a 16-bit constant.

[Matt Turner]

Gen8+ support was just broken, since MUL now consumes 32-bits from both
sources. Fixes 986 piglit tests on my BDW.

total instructions in shared programs: 8010869 -> 8010307 (-0.01%)
instructions in affected programs:     37244 -> 36682 (-1.51%)
helped:                                113
GAINED:                                97
---
 src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 24 +++++++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 266249f..05ac804 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -825,7 +825,29 @@ fs_visitor::nir_emit_alu(nir_alu_instr *instr)
       break;
 
    case nir_op_imul: {
-      /* TODO put in the 16-bit constant optimization once we have SSA */
+      if (brw->gen >= 8) {
+         emit(MUL(result, op[0], op[1]));
+         break;
+      } else {
+         nir_const_value *value0 = nir_src_as_const_value(instr->src[0].src);
+         nir_const_value *value1 = nir_src_as_const_value(instr->src[1].src);
+
+         if (value0 && value0->u[0] < (1 << 16)) {
+            if (brw->gen < 7) {
+               emit(MUL(result, op[0], op[1]));
+            } else {
+               emit(MUL(result, op[1], op[0]));
+            }
+            break;
+         } else if (value1 && value1->u[0] < (1 << 16)) {
+            if (brw->gen < 7) {
+               emit(MUL(result, op[1], op[0]));
+            } else {
+               emit(MUL(result, op[0], op[1]));
+            }
+            break;
+         }
+      }
 
       if (brw->gen >= 7)
          no16("SIMD16 explicit accumulator operands unsupported\n");
-- 
2.0.5