[Mesa-dev] [PATCH] i965/fs: Set pixel/sample mask for compute shaders atomic ops

[Matt Turner]

On Thu, Feb 19, 2015 at 3:42 PM, Jordan Justen
<jordan.l.justen at intel.com> wrote:
> For fragment programs, we pull this mask from the payload header. The same
> mask doesn't exist for compute shaders, so we set all bits to enabled.
>
> Note: this mask is ANDed with the execution mask, so some channels may not end
> up issuing the atomic operation.
>
> Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
> Cc: Ben Widawsky <ben at bwidawsk.net>
> Cc: Francisco Jerez <currojerez at riseup.net>
> ---
>  While it's fresh in our minds. :)
>
>  This seems to work for gen7 & gen8 CS. For CS simd16, we need the
>  0xffff change, but it seems to work fine for simd8 as well.
>
>  I also tested gen8 (simd8vs), and there were no piglit regressions.
>
>  src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> index 24cc118..960a0aa 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> @@ -2998,9 +2998,9 @@ fs_visitor::emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
>         * mask sent in the header to compute the actual set of channels that execute
>         * the atomic operation.
>         */
> -      assert(stage == MESA_SHADER_VERTEX);
> +      assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE);
>        emit(MOV(component(sources[0], 7),
> -               brw_imm_ud(0xff)))->force_writemask_all = true;
> +               brw_imm_ud(0xffff)))->force_writemask_all = true;

brw_imm_ud returns a brw_reg, which gets converted to an fs_reg with
type = HW_REG. That's not what we want (we consider HW_REGs to be
barriers to instruction scheduling, for instance). Change it to
fs_reg(0xffff) while you're modifying it.

>     }
>     length++;
>
> @@ -3061,9 +3061,9 @@ fs_visitor::emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
>         * mask sent in the header to compute the actual set of channels that execute
>         * the atomic operation.
>         */
> -      assert(stage == MESA_SHADER_VERTEX);
> +      assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE);
>        emit(MOV(component(sources[0], 7),
> -               brw_imm_ud(0xff)))->force_writemask_all = true;
> +               brw_imm_ud(0xffff)))->force_writemask_all = true;

Same thing here.

>     }
>
>     /* Set the surface read offset. */
> --
> 2.1.4
>
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