[Mesa-dev] [PATCH] i965/skl: Disable partial resolve in VC

[Ben Widawsky]

Recomendation [sic] is to set this field to 1 always. Programming it to default
value of 0, may have -ve impact on performance for MSAA WLs.

Another don't suck bit which needs to get set.

Totally untested.

Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
---
 src/mesa/drivers/dri/i965/brw_misc_state.c   |  9 +++++++++
 src/mesa/drivers/dri/i965/gen8_depth_state.c | 23 +++++++++++++++++++++--
 src/mesa/drivers/dri/i965/intel_reg.h        |  3 +--
 3 files changed, 31 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 190cdf7..1c6ca6a 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -878,6 +878,15 @@ brw_upload_invariant_state(struct brw_context *brw)
       ADVANCE_BATCH();
    }
 
+   if (brw->gen >= 9) {
+      BEGIN_BATCH(3);
+      OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
+      OUT_BATCH(GEN7_CACHE_MODE_1);
+      OUT_BATCH((GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC << 16) |
+                GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC);
+      ADVANCE_BATCH();
+   }
+
    if (brw->gen >= 8) {
       BEGIN_BATCH(3);
       OUT_BATCH(CMD_STATE_SIP << 16 | (3 - 2));
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index b4eb6e1..b29a79e 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -321,6 +321,18 @@ pma_fix_enable(const struct brw_context *brw)
            (kill_pixel && (depth_writes_enabled || stencil_writes_enabled)));
 }
 
+static inline uint32_t
+get_pma_stall_mask(struct brw_context *brw)
+{
+   if (brw->gen >= 9)
+      return (GEN8_HIZ_NP_PMA_FIX_ENABLE |
+              GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE |
+              GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC) << 16;
+   else
+      return (GEN8_HIZ_NP_PMA_FIX_ENABLE |
+              GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE) << 16;
+}
+
 static void
 write_pma_stall_bits(struct brw_context *brw, uint32_t pma_stall_bits)
 {
@@ -350,7 +362,7 @@ write_pma_stall_bits(struct brw_context *brw, uint32_t pma_stall_bits)
    BEGIN_BATCH(3);
    OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
    OUT_BATCH(GEN7_CACHE_MODE_1);
-   OUT_BATCH(GEN8_HIZ_PMA_MASK_BITS | pma_stall_bits);
+   OUT_BATCH(get_pma_stall_mask(brw) | pma_stall_bits);
    ADVANCE_BATCH();
 
    /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
@@ -371,6 +383,9 @@ gen8_emit_pma_stall_workaround(struct brw_context *brw)
    if (pma_fix_enable(brw))
       bits |= GEN8_HIZ_NP_PMA_FIX_ENABLE | GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE;
 
+   if (brw->gen >= 9)
+      bits |= GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC;
+
    write_pma_stall_bits(brw, bits);
 }
 
@@ -396,11 +411,15 @@ void
 gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
               unsigned int level, unsigned int layer, enum gen6_hiz_op op)
 {
+   uint16_t pma_stall_bits = 0;
    if (op == GEN6_HIZ_OP_NONE)
       return;
 
+   if (brw->gen >= 9)
+      pma_stall_bits |= GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC;
+
    /* Disable the PMA stall fix since we're about to do a HiZ operation. */
-   write_pma_stall_bits(brw, 0);
+   write_pma_stall_bits(brw, pma_stall_bits);
 
    assert(mt->first_level == 0);
    assert(mt->logical_depth0 >= 1);
diff --git a/src/mesa/drivers/dri/i965/intel_reg.h b/src/mesa/drivers/dri/i965/intel_reg.h
index af1c1df..31ef72f 100644
--- a/src/mesa/drivers/dri/i965/intel_reg.h
+++ b/src/mesa/drivers/dri/i965/intel_reg.h
@@ -144,5 +144,4 @@
 #define GEN7_CACHE_MODE_1               0x7004
 # define GEN8_HIZ_NP_PMA_FIX_ENABLE        (1 << 11)
 # define GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE (1 << 13)
-# define GEN8_HIZ_PMA_MASK_BITS \
-   ((GEN8_HIZ_NP_PMA_FIX_ENABLE | GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE) << 16)
+# define GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC (1 << 1)
-- 
2.3.1