[Mesa-dev] [PATCH 4/4] [v2] i965/hsw: Implement end of batch workaround

[Ben Widawsky]

v2: Sent out the wrong patch original. This patches switches the order of
flushes, doing the generic flush before the CC_STATE, and the required
workaround flush afterwards

Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
---
 src/mesa/drivers/dri/i965/intel_batchbuffer.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 7439cce..5bba453 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -32,6 +32,7 @@
 #include "intel_buffers.h"
 #include "intel_fbo.h"
 #include "brw_context.h"
+#include "brw_defines.h"
 
 static void
 intel_batchbuffer_reset(struct brw_context *brw);
@@ -231,6 +232,22 @@ brw_finish_batch(struct brw_context *brw)
    if (brw->batch.ring == RENDER_RING)
       brw_perf_monitor_finish_batch(brw);
 
+   if (brw->is_haswell) {
+      /* SW must program 3DSTATE_CC_STATE_POINTERS command at the end of every
+       * 3D batch buffer followed by a PIPE_CONTROL with RC flush and CS stall.
+       *
+       * From the example in the docs, it seems to expect a regular pipe control
+       * flush here as well. We may have done it already, but meh.
+       */
+      intel_batchbuffer_emit_mi_flush(brw);
+      BEGIN_BATCH(2);
+      OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
+      OUT_BATCH(brw->cc.state_offset | 1);
+      ADVANCE_BATCH();
+      brw_emit_pipe_control_flush(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH |
+                                       PIPE_CONTROL_CS_STALL);
+   }
+
    /* Mark that the current program cache BO has been used by the GPU.
     * It will be reallocated if we need to put new programs in for the
     * next batch.
-- 
2.3.1