[Mesa-dev] [RFC PATCH 04/40] i965/gen7.5: Implement MI_RS_STORE_DATA_IMM workaround for 3DPRIMITIVE commands

[Abdiel Janulgue]

Signed-off-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
---
 src/mesa/drivers/dri/i965/brw_draw.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index c581cc0..d48128d 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -254,6 +254,20 @@ static void brw_emit_prim(struct brw_context *brw,
 
 
    if (brw->gen >= 7) {
+      /* If resource streamer is enabled, an MI_RS_STORE_DATA_IMM with Resource
+       * Streamer Flush set must be programmed prior to a 3DPRIMITIVE command.
+       */
+      if (brw->has_resource_streamer) {
+         BEGIN_BATCH(4);
+         OUT_BATCH(MI_RS_STORE_DATA_IMM |
+                   (1 << 21) |  /* rs flush */
+                   (4 - 2));
+         OUT_BATCH(0);
+         OUT_BATCH(0);
+         OUT_BATCH(0);
+         ADVANCE_BATCH();
+      }
+      
       BEGIN_BATCH(7);
       OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2) | indirect_flag);
       OUT_BATCH(hw_prim | vertex_access_type);
-- 
1.9.1