[Mesa-dev] [RFC PATCH 14/40] i965: Initialize and partition a 32k constant buffer for uniforms.

[Abdiel Janulgue]

Uniforms are uploaded to this buffer instead of the space allocated from
the dynamic state base address.

This buffer is sliced into eight 4k-sized banks; each accessible
by SURFACE_STATE entries. These banks are layouted in such a way that all
shader stages can upload to whatever next free bank is available. This way,
we avoid generating numerous SURFACE_STATE entries everytime a uniform is
uploaded.

Using the gather table, we are able to refer to the constant entries using
the hw-binding table index plus the constant buffer offset to refer to
the constant data.

Signed-off-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
---
 src/mesa/drivers/dri/i965/brw_binding_tables.c | 31 ++++++++++++++++++++++++++
 src/mesa/drivers/dri/i965/brw_context.c        |  1 +
 src/mesa/drivers/dri/i965/brw_context.h        |  9 ++++++++
 3 files changed, 41 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_binding_tables.c b/src/mesa/drivers/dri/i965/brw_binding_tables.c
index b91e5d9..4138509 100644
--- a/src/mesa/drivers/dri/i965/brw_binding_tables.c
+++ b/src/mesa/drivers/dri/i965/brw_binding_tables.c
@@ -233,6 +233,33 @@ gen7_init_gather_pool(struct brw_context *brw)
                                                131072, 4096);
       brw->gather_pool.next_offset = 0;
    }
+
+   if (!brw->constants.bo) {
+      static const int cb_bank_size = 4096;
+      static const int num_cb_banks = 8;
+
+      brw->constants.bo = drm_intel_bo_alloc(brw->bufmgr, "constants_bo",
+                                             32768, 4096);
+      drm_intel_gem_bo_map_gtt(brw->constants.bo);
+      brw->constants.next_offset = 0;
+
+      assert(is_power_of_two(cb_bank_size));
+
+      uint32_t cb_offset = 0;
+      uint32_t surf_offset = 0;
+      for (int i = 0; i < num_cb_banks; i++) {
+         brw_create_constant_surface(brw, brw->constants.bo, cb_offset,
+                                     cb_bank_size,
+                                     &surf_offset, false);
+         cb_offset += cb_bank_size;
+         unsigned index = BRW_UNIFORM_GATHER_INDEX_START + i;
+
+         gen7_update_binding_table(brw, MESA_SHADER_VERTEX, index,
+                                   surf_offset);
+         gen7_update_binding_table(brw, MESA_SHADER_FRAGMENT, index,
+                                   surf_offset);
+      }
+   }
 }
 
 void
@@ -313,7 +340,11 @@ void
 gen7_reset_rs_pool_offsets(struct brw_context *brw)
 {
    brw->hw_bt_pool.next_offset = bt_size;
+   brw->constants.next_offset = 0;
    brw->gather_pool.next_offset = 0;
+
+   drm_intel_bo_unreference(brw->constants.bo);
+   brw->constants.bo = 0;
 }
 
 const struct brw_tracked_state gen7_hw_binding_tables = {
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 32bbdc2..d18733d 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -860,6 +860,7 @@ brwCreateContext(gl_api api,
 
    brw->hw_bt_pool.bo = 0;
    brw->gather_pool.bo = 0;
+   brw->constants.bo = 0;
 
    if (INTEL_DEBUG & DEBUG_SHADER_TIME)
       brw_init_shader_time(brw);
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index b205773..e2a6415 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -657,6 +657,9 @@ struct brw_vs_prog_data {
 
 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
 
+/** Start of hardware binding table index for uniform gather constant entries */
+#define BRW_UNIFORM_GATHER_INDEX_START 16
+
 /* Note: brw_gs_prog_data_compare() must be updated when adding fields to
  * this struct!
  */
@@ -1347,6 +1350,12 @@ struct brw_context
       uint32_t next_offset;
    } gather_pool;
 
+   /* Constant data shared by the shader stages */
+   struct {
+      drm_intel_bo *bo;
+      uint32_t next_offset;
+   } constants;
+
    struct {
       uint32_t state_offset;
       uint32_t blend_state_offset;
-- 
1.9.1