[Mesa-dev] [RFC PATCH 22/40] i965: Implement fine-grained uniform uploads

[Abdiel Janulgue]

Determine which shader stage changed their uniforms and only upload
uniforms which belong to it.

Signed-off-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
---
 src/mesa/drivers/dri/i965/brw_context.h   | 2 ++
 src/mesa/drivers/dri/i965/brw_program.c   | 9 +++++++++
 src/mesa/drivers/dri/i965/gen7_vs_state.c | 4 ++++
 3 files changed, 15 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index f384008..6706b4a 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1357,6 +1357,8 @@ struct brw_context
       uint32_t next_offset;
    } constants;
 
+   uint64_t uniformstagemap[MAX_UNIFORMS];
+
    struct {
       uint32_t state_offset;
       uint32_t blend_state_offset;
diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
index d9a3f05..c1eec8a 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -179,6 +179,14 @@ brwProgramStringNotify(struct gl_context *ctx,
    return true;
 }
 
+static void
+brw_uniform_update(struct gl_context *ctx, GLint location)
+{
+   struct brw_context *brw = brw_context(ctx);
+
+   brw->state.dirty.mesa |= brw->uniformstagemap[location];
+}
+
 void
 brw_add_texrect_params(struct gl_program *prog)
 {
@@ -236,6 +244,7 @@ void brwInitFragProgFuncs( struct dd_function_table *functions )
 
    functions->NewShader = brw_new_shader;
    functions->LinkShader = brw_link_shader;
+   functions->UniformUpdate = brw_uniform_update;
 }
 
 void
diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c b/src/mesa/drivers/dri/i965/gen7_vs_state.c
index 85bd56f..269612b 100644
--- a/src/mesa/drivers/dri/i965/gen7_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_vs_state.c
@@ -70,6 +70,10 @@ gen7_upload_constant_buffer_data(struct brw_context* brw,
       _NEW_FRAGMENT_CONSTANTS
    };
 
+   if (!(brw->state.dirty.brw & BRW_NEW_BATCH) &&
+       (!prog_data->nr_params || !(brw->state.dirty.mesa & const_state_stage[stage_state->stage])))
+      return;
+
    /* If current constant data does not fit in current constant buffer bank,
     * move to next slot. 
     */
-- 
1.9.1