[Mesa-dev] [PATCH 00/13] RadeonSI cache flushing improvements for CIK

[Michel Dänzer]

On 06.01.2015 05:20, Marek Olšák wrote:
> Hi,
> 
> The motivation for this patch series is to reduce the number of TC L2
> cache flushes.
> 
> The result is that TC L2 is only flushed at IB boundary and when the
> framebuffer is changed. This is achieved by switching all clients to
> use the cache, so that all data is coherent between clients. In this
> case, only CP DMA needs to be switched. Shaders and WRITE_DATA
> already use it. Index buffers can't use the cache, so they are
> handled as a special case in the code. That is for CIK.
> 
> As far as SI is concerned, CP DMA can't use TC L2. Only WRITE_DATA
> can and it does use the cache at the moment, which could produce
> corrupted resource descriptors in theory. (mixing uncached CP DMA and
> cached WRITE_DATA without flushes in between for updating descriptors
> is certainly unsafe) This is fixed in this series too as well as
> other things I discovered.
> 
> Please review.

Looks like great work, Marek. The series is

Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>


-- 
Earthling Michel Dänzer               |               http://www.amd.com
Libre software enthusiast             |             Mesa and X developer