[Mesa-dev] [PATCH] radeon: fix r600/7 fmask pitch

[Dave Airlie]

On 8 January 2015 at 11:25, Alex Deucher <alexdeucher at gmail.com> wrote:
> On Wed, Jan 7, 2015 at 8:19 PM, Dave Airlie <airlied at gmail.com> wrote:
>> Okay I've been doing some further FMASK studies empirically, dumping
>> the fmask after rendering to an MSAA surface,
>>
>> it appears on r600 at 8xMSAA, every 8x8 tile requires 128 bytes of
>> storage, that is used depending on the value in the CMASK.
>>
>> So it appears at 8xMSAA for every 4-bit entry in the CMASK we need to
>> allocate 128-bytes in the FMASK, now the FMASK appears to tile the
>> CMASK entries as well inside a macrotile layout.
>>
>> At this point I think the tiling docs I have are just wrong for r600,
>> as they state at 8xMSAA with 8x8 tile, it should be w*h*(samples / 8)
>> *log2(samples) which for me is 8x8x1x3, which is 196 bytes, which
>> clearly the hw isn't doing.
>>
>> Anyone from AMD have more accurate info or should I just hack this, I
>> get the feeling overallocating the FMASK is better than what we do now
>> anyways.
>
> I can dig around a bit, but most of the r600 stuff is not really fresh
> in anyone's mind.  I'm fine with just overallocating it at this point.

At this point I'm starting to think I've no idea how this works at all.

The fmask fields are interleaved somehow as well.

So if you get a CMASK with 0xf in it which means 3 bits, then
things do indeed seem to use 196-byte fields,

however in that case I'd have expected to never see anything
in the 196-256 byte range, but I do depending on how things
end up.

Colour me very confused on how this hw works at all.

I suspect evergreen/cayman just happen to allocate
a large enough size my sheer luck at this point.

Dave.